mitya1337 / Simple_I2CLinks
Simple implementation of I2C interface written on Verilog and SystemC
☆42Updated 7 years ago
Alternatives and similar repositories for Simple_I2C
Users that are interested in Simple_I2C are comparing it to the libraries listed below
Sorting:
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- ☆38Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- I2C controller core☆43Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆82Updated 5 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- Python Tool for UVM Testbench Generation☆52Updated last year
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- Basic RISC-V Test SoC☆128Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆61Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago