nmi-leipzig / sim-x-pllLinks
Verilog based simulation modell for 7 Series PLL
☆13Updated 5 years ago
Alternatives and similar repositories for sim-x-pll
Users that are interested in sim-x-pll are comparing it to the libraries listed below
Sorting:
- gateware for the main fpga, including a hispi decoder and image processing☆13Updated 6 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- ☆22Updated 3 weeks ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 10 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Updated 4 years ago
- ☆18Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆19Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- Small footprint and configurable HyperBus core☆12Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆21Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆46Updated 6 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 5 months ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Updated last week
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago