nmi-leipzig / sim-x-pll
Verilog based simulation modell for 7 Series PLL
☆12Updated 4 years ago
Alternatives and similar repositories for sim-x-pll:
Users that are interested in sim-x-pll are comparing it to the libraries listed below
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆17Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 6 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆12Updated 6 years ago
- PicoRV☆44Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last week
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- ☆22Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- USB virtual model in C++ for Verilog☆28Updated 3 months ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- ☆12Updated 3 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Updated 3 years ago
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- AXI Formal Verification IP☆20Updated 3 years ago
- A Verilog Synthesis Regression Test☆35Updated 9 months ago
- ☆21Updated last week
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆26Updated 11 years ago
- A padring generator for ASICs☆24Updated last year
- Experiments with Yosys cxxrtl backend☆47Updated this week
- ☆12Updated 3 weeks ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- cocotb extension for nMigen☆15Updated 2 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆16Updated 6 years ago
- An Open Source Link Protocol and Controller☆24Updated 3 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆13Updated last week
- 👾 Design ∪ Hardware☆72Updated 2 months ago
- Small footprint and configurable HyperBus core☆10Updated 2 years ago