Alternatives and similar repositories for sim-x-pll

Users that are interested in sim-x-pll are comparing it to the libraries listed below

• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• apertus-open-source-cinema / axiom-micro-gateware
  gateware for the main fpga, including a hispi decoder and image processing
  ☆13Updated 7 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 5 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated 3 weeks ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆49Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆30Updated last month
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• mattvenn / logo-to-gds2
  ☆18Updated 3 years ago
• enjoy-digital / litesata_axiom
  ☆13Updated 4 years ago
• GuzTech / vivado-picorv32
  A Vivado IP package of the PicoRV32 RISC-V processor
  ☆15Updated 5 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆97Updated last year
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆32Updated 5 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• chipsalliance / f4pga-xc7-bram-patch
  Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
  ☆19Updated 3 years ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆30Updated 12 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• mattvenn / simulate-gate
  Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
  ☆14Updated 5 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago