shifengzhicheng / Fudan_Digital_EDALinks
复旦数字集成电路设计自动化项目文档
☆8Updated 3 months ago
Alternatives and similar repositories for Fudan_Digital_EDA
Users that are interested in Fudan_Digital_EDA are comparing it to the libraries listed below
Sorting:
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆100Updated 3 weeks ago
- commit rtl and build cosim env☆35Updated last year
- this repository is vim cfg for verilog.☆50Updated 11 months ago
- ☆51Updated 2 months ago
- ☆148Updated last week
- CPU Design Based on RISCV ISA☆117Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year
- 在vscode上的数字设计开发插件☆383Updated 2 years ago
- AMBA bus lecture material☆452Updated 5 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆93Updated 3 years ago
- Vivado诸多IP,包括图像处理等☆209Updated 11 months ago
- 2023集创赛紫光同创杯一等奖项目☆119Updated last year
- automatic-verilog based on vimscript☆266Updated last year
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- practice configure AHB-Lite bus protocol☆14Updated 6 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- 数字IC设计 学习笔记☆149Updated 3 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆142Updated 5 years ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆408Updated last year
- AXI协议规范中文翻译版☆154Updated 3 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Updated 2 years ago
- HDLBits website practices & solutions☆744Updated last year
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- AXI总线连接器☆101Updated 5 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆209Updated 2 years ago
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆521Updated 4 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆185Updated 8 months ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆186Updated last year