edwardcwang / chisel-template-liteLinks
Lightweight Chisel template
☆13Updated 5 years ago
Alternatives and similar repositories for chisel-template-lite
Users that are interested in chisel-template-lite are comparing it to the libraries listed below
Sorting:
- Coarse Grained Reconfigurable Array☆20Updated 3 weeks ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆126Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- Next generation CGRA generator☆116Updated this week
- Ariane is a 6-stage RISC-V CPU☆151Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆124Updated this week
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform☆12Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 weeks ago
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆31Updated 3 years ago
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆142Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- BlackParrot on Zynq☆47Updated last week
- Floating point modules for CHISEL☆31Updated 11 years ago