vitaliikulin / I2C-FPGA-Verilog-HDLLinks
In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.
☆19Updated 5 years ago
Alternatives and similar repositories for I2C-FPGA-Verilog-HDL
Users that are interested in I2C-FPGA-Verilog-HDL are comparing it to the libraries listed below
Sorting:
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22Updated 2 years ago
- Hardware implementation of HDR image producing algorithm☆16Updated 3 years ago
- FPGA纯逻辑实现modbus通信☆22Updated 3 years ago
- ⚙️ 基于 Zynq-7 全可编程 SoC 的设计☆36Updated 3 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆56Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆60Updated 5 years ago
- The SoC Design for Time-Sensitive Networking (TSN)☆20Updated last month
- Interface Protocol in Verilog☆50Updated 6 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 7 years ago
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆73Updated 3 years ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆27Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- 【例程】国产高云FPGA 开发板及其工程☆36Updated last year
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Gigabit Ethernet UDP communication driver☆79Updated 6 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Updated 7 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆60Updated 3 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆47Updated 8 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆94Updated 8 years ago
- SPI interface connect to APB BUS with Verilog HDL☆37Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆66Updated 3 years ago