ydnatag / nmigen-cocotb
cocotb extension for nMigen
☆15Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for nmigen-cocotb
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- USB virtual model in C++ for Verilog☆28Updated 3 weeks ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- ☆29Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- A padring generator for ASICs☆22Updated last year
- ☆39Updated last year
- assorted library of utility cores for amaranth HDL☆81Updated last month
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 8 months ago
- Virtual development board for HDL design☆39Updated last year
- Small footprint and configurable HyperBus core☆10Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆36Updated last year
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆11Updated 7 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆19Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆28Updated this week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- Interfacing VHDL and foreign languages with VUnit☆14Updated 4 years ago
- sample VCD files☆36Updated 8 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆53Updated this week
- Open Source Verification Bundle for VHDL and System Verilog☆40Updated 9 months ago
- Python script to transform a VCD file to wavedrom format☆73Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- VHDL String Formatting Library☆23Updated 6 months ago
- Example of Test Driven Design with VUnit☆14Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated this week
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆47Updated this week