ydnatag / nmigen-cocotbLinks
cocotb extension for nMigen
☆16Updated 3 years ago
Alternatives and similar repositories for nmigen-cocotb
Users that are interested in nmigen-cocotb are comparing it to the libraries listed below
Sorting:
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆92Updated 8 months ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆21Updated last week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- ☆34Updated 4 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 2 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 6 months ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Updated 4 years ago
- ☆33Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year