ydnatag / nmigen-cocotb
cocotb extension for nMigen
☆15Updated 2 years ago
Alternatives and similar repositories for nmigen-cocotb:
Users that are interested in nmigen-cocotb are comparing it to the libraries listed below
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆32Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- USB virtual model in C++ for Verilog☆29Updated 3 months ago
- A padring generator for ASICs☆24Updated last year
- Small footprint and configurable HyperBus core☆10Updated 2 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 10 months ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- assorted library of utility cores for amaranth HDL☆85Updated 4 months ago
- Virtual development board for HDL design☆40Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆35Updated last month
- ☆33Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated last week
- System on Chip toolkit for Amaranth HDL☆86Updated 3 months ago
- ☆22Updated 2 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- Flip flop setup, hold & metastability explorer tool☆32Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Small footprint and configurable Inter-Chip communication cores☆54Updated 3 weeks ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆21Updated 3 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated 2 weeks ago
- PicoRV☆44Updated 4 years ago
- ☆36Updated 2 years ago