cocotb extension for nMigen
☆17Feb 26, 2022Updated 4 years ago
Alternatives and similar repositories for nmigen-cocotb
Users that are interested in nmigen-cocotb are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 2 years ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆29Feb 25, 2026Updated 3 weeks ago
- assorted library of utility cores for amaranth HDL☆103Sep 17, 2024Updated last year
- command line tool for frequent amaranth HDL tasks (generate sources, show design)☆18Dec 27, 2021Updated 4 years ago
- USB Full-Speed core written in migen/LiteX☆12Sep 19, 2019Updated 6 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- A configurable USB 2.0 device core☆32Jun 12, 2020Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- System on Chip toolkit for Amaranth HDL☆100Mar 3, 2026Updated 2 weeks ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Jul 28, 2025Updated 7 months ago
- I want to learn [n]Migen.☆44Jan 26, 2020Updated 6 years ago
- A Python to VHDL compiler☆17Apr 28, 2025Updated 10 months ago
- Using the TinyFPGA BX USB code in user designs☆52Jan 31, 2019Updated 7 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45May 25, 2025Updated 9 months ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 2 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆34Aug 27, 2024Updated last year
- ☆37Sep 19, 2024Updated last year
- ☆14Aug 27, 2020Updated 5 years ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆52Mar 5, 2026Updated 2 weeks ago
- Awesome projects using the Amaranth HDL☆20Feb 6, 2025Updated last year
- Python interface for cross-calling with HDL☆49Mar 14, 2026Updated last week
- SPI flash MITM and emulation (QSPI is a WIP)☆20Jan 27, 2022Updated 4 years ago
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 5 years ago
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆97Feb 20, 2025Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Top level CedarEDA integration package☆28Oct 22, 2024Updated last year
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- Rust Test Bench - write HDL tests in Rust.☆24Nov 28, 2022Updated 3 years ago
- ☆44Mar 12, 2025Updated last year
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- Kicad Library to pretify your schematic with pride flags.☆16Nov 13, 2022Updated 3 years ago
- an experimental SDR platform☆44Feb 8, 2023Updated 3 years ago
- nMigen support for Xilinx Zynq devices☆15Nov 5, 2022Updated 3 years ago