ethanelle / Branch-Predictors
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
☆13Updated 6 years ago
Alternatives and similar repositories for Branch-Predictors:
Users that are interested in Branch-Predictors are comparing it to the libraries listed below
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆65Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- ☆29Updated 3 weeks ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆67Updated this week
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆19Updated 4 years ago
- Championship Branch Prediction 2025☆40Updated 3 weeks ago
- ☆26Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆25Updated 2 weeks ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 5 years ago
- ☆91Updated last year
- gem5 repository to study chiplet-based systems☆72Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Heterogeneous simulator for DECADES Project☆32Updated 11 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆34Updated 3 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- ☆30Updated 10 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- CGRA framework with vectorization support.☆29Updated this week
- ☆23Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- ☆20Updated last year
- ☆15Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- ☆59Updated last year