luunguyen97 / DPU-TRD-ZCU104
☆12Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for DPU-TRD-ZCU104
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- PYNQ Composabe Overlays☆67Updated 5 months ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆22Updated 5 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆67Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆32Updated 2 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- ☆60Updated 5 years ago
- Zynq-7000 DPU TRD☆43Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆54Updated 3 months ago
- A systolic array matrix multiplier☆23Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆63Updated last year
- Verilog implementation of Softmax function☆48Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆26Updated 2 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆33Updated 3 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆102Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- ☆93Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆9Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- ☆26Updated 5 years ago
- round robin arbiter☆68Updated 10 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆16Updated 7 months ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆80Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- An LeNet RTL implement onto FPGA☆39Updated 6 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago