Alternatives and similar repositories for awesome-opensource-hardware-repos

Users that are interested in awesome-opensource-hardware-repos are comparing it to the libraries listed below

• aolofsson / awesome-semiconductor-startups
  List of awesome semiconductor startups
  ☆682Updated 4 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆364Updated 2 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆220Updated last month
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆369Updated 9 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆310Updated 10 months ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆96Updated 9 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆306Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆249Updated last year
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆395Updated last month
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆188Updated this week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆223Updated 9 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆332Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated last week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆572Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated 2 weeks ago
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆304Updated this week
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆278Updated 10 months ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆229Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆298Updated this week
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆312Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆436Updated 3 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated 3 weeks ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆164Updated last week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆303Updated this week
• chipsalliance / Cores-VeeR-EH2
  ☆250Updated 2 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆624Updated last month
• os-fpga / Virtual-FPGA-Lab
  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…
  ☆232Updated 6 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 8 months ago