List of awesome open source hardware projects
☆360Jan 2, 2023Updated 3 years ago
Alternatives and similar repositories for awesome-opensource-hardware-repos
Users that are interested in awesome-opensource-hardware-repos are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- List of awesome open source hardware tools, generators, and reusable designs☆2,428Mar 2, 2026Updated 6 months ago
- List of awesome semiconductor startups☆776Sep 2, 2026Updated 3 weeks ago
- ☆33Jan 24, 2020Updated 6 years ago
- Modular hardware build system☆1,217Updated this week
- ☆44Jan 26, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆414Apr 13, 2023Updated 3 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆625Jan 3, 2026Updated 8 months ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆53Jul 21, 2022Updated 4 years ago
- Common SystemVerilog components☆800Updated this week
- Fully opensource spiking neural network accelerator☆178Feb 13, 2023Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆42Jun 10, 2021Updated 5 years ago
- Hardware Description Languages☆1,175Jul 9, 2026Updated 2 months ago
- Verilog library for ASIC and FPGA designers☆1,441May 8, 2024Updated 2 years ago
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆25Jun 23, 2024Updated 2 years ago
- 100 Days of RTL☆427Aug 15, 2024Updated 2 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,943Mar 25, 2026Updated 5 months ago
- An Open-source FPGA IP Generator☆1,154Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆633Updated this week
- A modular hardware abstraction library☆53Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆130Jun 11, 2024Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆86Jul 17, 2026Updated 2 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆241Sep 4, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- BaseJump STL: A Standard Template Library for SystemVerilog☆684Updated this week
- Code generation tool for control and status registers☆471Sep 11, 2026Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆281Nov 6, 2024Updated last year
- An open-source static random access memory (SRAM) compiler.☆1,136Aug 16, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,887Aug 25, 2026Updated 3 weeks ago
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated 2 years ago
- The OpenPiton Platform☆828Feb 25, 2026Updated 6 months ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 7 months ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog package manager written in Rust☆147Oct 5, 2024Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆326Aug 7, 2026Updated last month
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆297Jun 18, 2026Updated 3 months ago
- The UVM written in Python☆570Updated this week
- Filter builder tool☆18Apr 11, 2022Updated 4 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆123Updated this week