List of awesome semiconductor startups
☆771May 30, 2026Updated 2 months ago
Alternatives and similar repositories for awesome-semiconductor-startups
Users that are interested in awesome-semiconductor-startups are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- List of awesome open source hardware tools, generators, and reusable designs☆2,385Mar 2, 2026Updated 5 months ago
- List of awesome open source hardware projects☆360Jan 2, 2023Updated 3 years ago
- Modular hardware build system☆1,194Updated this week
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆957Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆789Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An open-source static random access memory (SRAM) compiler.☆1,106Jul 18, 2026Updated 2 weeks ago
- repository for a bandgap voltage reference in SKY130 technology☆44Jan 20, 2023Updated 3 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆293Jun 18, 2026Updated last month
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 9 years ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆486Updated this week
- ☆44Jan 26, 2020Updated 6 years ago
- ☆410Apr 13, 2023Updated 3 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆616Jan 3, 2026Updated 7 months ago
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆223Jun 19, 2026Updated last month
- Interchange formats for chip design.☆39Feb 15, 2026Updated 5 months ago
- ☆376Jul 5, 2026Updated 3 weeks ago
- Verilog package manager written in Rust☆147Oct 5, 2024Updated last year
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,628Jul 21, 2026Updated last week
- An abstraction library for interfacing EDA tools☆783Jul 2, 2026Updated last month
- Communication framework for RTL simulation and emulation.☆315Jul 27, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆677Jul 7, 2026Updated 3 weeks ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,878Mar 25, 2026Updated 4 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A library of open PDK packages☆123Jul 21, 2026Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆123Apr 1, 2024Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆52Jan 13, 2021Updated 5 years ago
- Netlist API (and more) for EDA flow development☆155Updated this week
- Demo: how to create a custom EBRICK☆27Nov 20, 2024Updated last year
- ☆180Sep 11, 2022Updated 3 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆436Updated this week
- 100 Days of RTL☆423Aug 15, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,443Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆365Dec 2, 2025Updated 8 months ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆138Jun 10, 2026Updated last month
- Parasitic Extraction for KLayout☆45Updated this week
- Code generation tool for control and status registers☆464Jul 16, 2026Updated 2 weeks ago
- Hardware Description Languages☆1,164Jul 9, 2026Updated 3 weeks ago
- Blender GDSII Importer with PDK Support☆138Jul 16, 2026Updated 2 weeks ago
- Online viewer of Xschem schematic files☆33Dec 14, 2025Updated 7 months ago