Alternatives and similar repositories for learn-fpga-amaranth:

Users that are interested in learn-fpga-amaranth are comparing it to the libraries listed below

• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆89Updated 6 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆166Updated last year
• pieter3d / simview
  ☆77Updated last year
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆87Updated 6 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆174Updated last month
• olofk / corescore
  CoreScore
  ☆146Updated 2 months ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆98Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆86Updated 5 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• RobertBaruch / amaranth-tutorial
  ☆40Updated 2 years ago
• fjullien / migen_litex_tutorials
  ☆107Updated 2 years ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• vmunoz82 / eda_tools
  A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …
  ☆43Updated last year
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆112Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 2 months ago
• efabless / clear
  ☆66Updated 7 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆141Updated 5 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆61Updated last week
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆66Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆229Updated 5 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆111Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆88Updated 2 weeks ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆155Updated 2 weeks ago
• openXC7 / demo-projects
  Demo projects for various Kintex FPGA boards
  ☆51Updated 10 months ago