bl0x / learn-fpga-amaranth
Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
☆89Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for learn-fpga-amaranth
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆157Updated 8 months ago
- ☆97Updated last year
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆94Updated last year
- Naive Educational RISC V processor☆74Updated last month
- ☆76Updated 8 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆73Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆48Updated last week
- Documenting the Lattice ECP5 bit-stream format.☆51Updated last year
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆41Updated last year
- Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…☆46Updated 3 weeks ago
- A pipelined RISC-V processor☆48Updated 11 months ago
- RISC-V Processor written in Amaranth HDL☆33Updated 2 years ago
- Example LED blinking project for your FPGA dev board of choice☆165Updated 3 months ago
- Experimental flows using nextpnr for Xilinx devices☆39Updated this week
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆112Updated 2 weeks ago
- assorted library of utility cores for amaranth HDL☆81Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆66Updated this week
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- Waveform Viewer Extension for VScode☆75Updated this week
- FuseSoC standard core library☆115Updated last month
- Nitro USB FPGA core☆83Updated 8 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆63Updated this week
- System on Chip toolkit for Amaranth HDL☆84Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Virtual Development Board☆58Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆70Updated 7 months ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆140Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆151Updated 7 months ago