alexplusplus / DW-Nicos-Weg-A1View external linksLinks
Translation of DW's telenovela scripts into English and Russian https://www.youtube.com/playlist?list=PLs7zUO7VPyJ5DV1iBRgSw2uDl832n0bLg
☆18May 5, 2018Updated 7 years ago
Alternatives and similar repositories for DW-Nicos-Weg-A1
Users that are interested in DW-Nicos-Weg-A1 are comparing it to the libraries listed below
Sorting:
- NoC simulation using gem5 (a simple tul)☆14Mar 23, 2024Updated last year
- Online documentation can be found at https://minres.github.io/SCViewer/☆21Feb 11, 2024Updated 2 years ago
- EE577b-Course-Project☆19May 6, 2020Updated 5 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Dec 22, 2023Updated 2 years ago
- Criticality-aware Framework for Modeling Computer Performance☆33Dec 15, 2024Updated last year
- ☆29Oct 20, 2019Updated 6 years ago
- ☆38Oct 21, 2025Updated 3 months ago
- A scalable Eyeriss model in SystemC.☆33Jan 1, 2023Updated 3 years ago
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆34Feb 11, 2026Updated last week
- Public contribution for Microsoft Style Guide☆27Mar 11, 2019Updated 6 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago
- A Node.js style checker and lint tool for Markdown/CommonMark files.☆28Apr 2, 2019Updated 6 years ago
- Eyeriss chip simulator☆39Mar 6, 2020Updated 5 years ago
- ☆39Oct 22, 2012Updated 13 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆73Sep 29, 2025Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆75Feb 9, 2026Updated last week
- ☆64Mar 16, 2018Updated 7 years ago
- OpenAI ChatGPT for Android☆88Mar 31, 2023Updated 2 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- The official python tutorial in other formats☆92Feb 8, 2019Updated 7 years ago
- ☆124Jul 22, 2020Updated 5 years ago
- 翻译漫谈——我的翻译经验总结☆118Mar 28, 2019Updated 6 years ago
- Yomitan-compatible dictionaries from wikitionary data☆152Feb 4, 2026Updated 2 weeks ago
- some pocs for antivirus evasion☆129Aug 28, 2023Updated 2 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162May 1, 2022Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Dec 14, 2019Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆189Nov 18, 2024Updated last year
- RISC-V Virtual Prototype☆185Dec 13, 2024Updated last year
- Modeling Architectural Platform☆219Updated this week
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- ☆239Apr 8, 2024Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆201Apr 14, 2024Updated last year
- Async HTTP for Humans, coroutine Requests☆209Aug 14, 2023Updated 2 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆218Dec 22, 2020Updated 5 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆295Sep 14, 2023Updated 2 years ago
- RISC-V SystemC-TLM simulator☆338Nov 8, 2025Updated 3 months ago