Translation of DW's telenovela scripts into English and Russian https://www.youtube.com/playlist?list=PLs7zUO7VPyJ5DV1iBRgSw2uDl832n0bLg
☆20May 5, 2018Updated 8 years ago
Alternatives and similar repositories for DW-Nicos-Weg-A1
Users that are interested in DW-Nicos-Weg-A1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Oct 8, 2021Updated 4 years ago
- ☆15Feb 2, 2026Updated 6 months ago
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Apr 10, 2026Updated 4 months ago
- MATLAB Vision HDL☆16Jan 17, 2020Updated 6 years ago
- A short tutorial on Gem5 with focus on how to run and modify Garnet2.0☆17Apr 18, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- EE577b-Course-Project☆19May 6, 2020Updated 6 years ago
- A simple NES/Famicom emulator☆26Mar 3, 2019Updated 7 years ago
- Criticality-aware Framework for Modeling Computer Performance☆34Dec 15, 2024Updated last year
- A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for arc…☆16Feb 10, 2026Updated 6 months ago
- A Game Boy emulator written in C++/SystemC TLM-2.0☆37Jun 29, 2026Updated last month
- ☆29Oct 20, 2019Updated 6 years ago
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆36Jul 23, 2026Updated 2 weeks ago
- A scalable Eyeriss model in SystemC.☆35Jan 1, 2023Updated 3 years ago
- ☆28Feb 28, 2026Updated 5 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Sep 22, 2018Updated 7 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Jul 12, 2018Updated 8 years ago
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 6 years ago
- CQU Dual Issue Machine☆42Jun 23, 2024Updated 2 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Jul 21, 2022Updated 4 years ago
- Eyeriss chip simulator☆41Mar 6, 2020Updated 6 years ago
- PKU computer organization and architecture RISC-V Simulator LAB☆38Sep 18, 2018Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆45Aug 10, 2022Updated 4 years ago
- ☆42Jul 28, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆70Dec 18, 2024Updated last year
- ☆44Oct 21, 2025Updated 9 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆63Dec 3, 2021Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆99Jan 5, 2025Updated last year
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆89Apr 28, 2024Updated 2 years ago
- AXI总线连接器☆109Mar 26, 2020Updated 6 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆133Dec 17, 2023Updated 2 years ago
- ☆126Jul 2, 2022Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆128Jul 22, 2020Updated 6 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆167May 1, 2022Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆150Jun 23, 2024Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆196Nov 18, 2024Updated last year
- RISC-V Virtual Prototype☆191Jul 21, 2026Updated 2 weeks ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler …☆185Dec 14, 2019Updated 6 years ago
- Modeling Architectural Platform☆227Updated this week