Online documentation can be found at https://minres.github.io/SCViewer/
☆22Apr 10, 2026Updated 2 months ago
Alternatives and similar repositories for SCViewer
Users that are interested in SCViewer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Public repository for PySysC, (From SC Common Practices Subgroup)☆55Dec 26, 2023Updated 2 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆136Updated this week
- Die App zum Lernen auf die Amateurfunkprüfung passend zu 50ohm.de☆29Apr 19, 2026Updated 2 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆310Jun 19, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆90Apr 13, 2026Updated 2 months ago
- An App as Offline Frontend for CloudLog☆28Jan 24, 2026Updated 5 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆31Jul 29, 2020Updated 5 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated last year
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- Xtext project to parse CoreDSL files☆23Apr 29, 2026Updated 2 months ago
- RISC-V SystemC-TLM simulator☆354Feb 20, 2026Updated 4 months ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16May 18, 2026Updated last month
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Amateur Radio Callsign RegEx Generator☆15Jul 12, 2022Updated 3 years ago
- Computer architecture project : Cache simulator with LRU replacement policy☆12Jul 27, 2021Updated 4 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- Mini17 - QRP M17 handheld☆41Jan 30, 2026Updated 4 months ago
- ☆10Oct 8, 2021Updated 4 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆34Oct 15, 2024Updated last year
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 7 months ago
- Automatic upload of ADIF log to CloudLog☆14Mar 10, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A Game Boy emulator written in C++/SystemC TLM-2.0☆36Updated this week
- a collection of antenna related designs (mostly based on the UniBalun Project)☆15Nov 7, 2023Updated 2 years ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- Instant Neural Graphics Primitives from scratch, zero dependencies. Learning by doing.☆10Aug 18, 2023Updated 2 years ago
- A C-family AST implementation designed to be an IR for DSL compilers.☆17Jul 6, 2017Updated 8 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- ☆14Jul 14, 2015Updated 10 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- A standalone structural (gate-level) verilog parser☆41Mar 20, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆18Aug 23, 2021Updated 4 years ago
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆35May 22, 2026Updated last month
- documentation and code for a Python PEP about an appoximate equal check for Python☆17Jun 29, 2015Updated 11 years ago
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆89Apr 17, 2026Updated 2 months ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- Making cocotb testbenches that bit easier☆39Feb 28, 2026Updated 4 months ago