Alternatives and similar repositories for SCViewer

Users that are interested in SCViewer are comparing it to the libraries listed below

• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆32Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆20Updated 8 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 6 months ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆27Updated last month
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated 2 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆42Updated this week
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated 2 weeks ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆16Updated 5 months ago
• pulp-platform / svase
  ☆33Updated 10 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆30Updated last year
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆52Updated 2 years ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 5 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆47Updated 3 weeks ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 weeks ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆32Updated 2 weeks ago
• avidan-efody / pyreg
  Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python
  ☆11Updated 3 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated 2 weeks ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆131Updated last week
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆48Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago