Online documentation can be found at https://minres.github.io/SCViewer/
☆21Apr 10, 2026Updated last month
Alternatives and similar repositories for SCViewer
Users that are interested in SCViewer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Die App zum Lernen auf die Amateurfunkprüfung passend zu 50ohm.de☆28Apr 19, 2026Updated last month
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆308May 19, 2026Updated 3 weeks ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆90Apr 13, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An App as Offline Frontend for CloudLog☆28Jan 24, 2026Updated 4 months ago
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated last year
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- Xtext project to parse CoreDSL files☆23Apr 29, 2026Updated last month
- ☆23Feb 18, 2025Updated last year
- RISC-V SystemC-TLM simulator☆352Feb 20, 2026Updated 3 months ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16May 18, 2026Updated 3 weeks ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- Computer architecture project : Cache simulator with LRU replacement policy☆12Jul 27, 2021Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- Mini17 - QRP M17 handheld☆41Jan 30, 2026Updated 4 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆33Oct 15, 2024Updated last year
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 7 months ago
- Automatic upload of ADIF log to CloudLog☆14Mar 10, 2025Updated last year
- A Game Boy emulator written in C++/SystemC TLM-2.0☆36Updated this week
- a collection of antenna related designs (mostly based on the UniBalun Project)☆15Nov 7, 2023Updated 2 years ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Instant Neural Graphics Primitives from scratch, zero dependencies. Learning by doing.☆10Aug 18, 2023Updated 2 years ago
- A C-family AST implementation designed to be an IR for DSL compilers.☆17Jul 6, 2017Updated 8 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- ☆14Jul 14, 2015Updated 10 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- A standalone structural (gate-level) verilog parser☆41Mar 20, 2026Updated 2 months ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆18Aug 23, 2021Updated 4 years ago
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆35May 22, 2026Updated 2 weeks ago
- documentation and code for a Python PEP about an appoximate equal check for Python☆17Jun 29, 2015Updated 10 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆88Apr 17, 2026Updated last month
- ☆16May 7, 2025Updated last year
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- Making cocotb testbenches that bit easier☆39Feb 28, 2026Updated 3 months ago
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆40Mar 11, 2026Updated 2 months ago