Library for modelling performance costs of different Neural Network workloads on NPU devices
☆34Feb 11, 2026Updated 3 weeks ago
Alternatives and similar repositories for npu-nn-cost-model
Users that are interested in npu-nn-cost-model are comparing it to the libraries listed below
Sorting:
- ☆20Nov 27, 2025Updated 3 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆31Aug 28, 2025Updated 6 months ago
- ☆10Oct 8, 2021Updated 4 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Feb 27, 2026Updated last week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- NoC simulation using gem5 (a simple tul)☆14Mar 23, 2024Updated last year
- OpenVINO Intel NPU Compiler☆83Updated this week
- Online documentation can be found at https://minres.github.io/SCViewer/☆21Feb 11, 2024Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- A fork of Xiangshan for AI☆36Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- GPP CPassword Decryption Tools☆12Jun 13, 2022Updated 3 years ago
- Intel® NPU Acceleration Library☆709Apr 24, 2025Updated 10 months ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Autocomp: AI-Driven Code Optimizer for Tensor Accelerators☆74Feb 24, 2026Updated last week
- Download images and convert it to pdf (NSFW: A+)☆14Mar 29, 2025Updated 11 months ago
- ☆29Oct 20, 2019Updated 6 years ago
- Criticality-aware Framework for Modeling Computer Performance☆33Dec 15, 2024Updated last year
- A Rocket-based RISC-V superscalar in-order core☆38Feb 24, 2026Updated last week
- ☆12Aug 12, 2022Updated 3 years ago
- A scalable Eyeriss model in SystemC.☆33Jan 1, 2023Updated 3 years ago
- Vstream - Video Analytics pipeline with Hardware based accelerations (dev - stage)☆10Feb 2, 2024Updated 2 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- CQU Dual Issue Machine☆38Jun 23, 2024Updated last year
- ROACH2 hardware gerbers, layout and bom☆11May 31, 2013Updated 12 years ago
- Performant source for RPM repositories metadata https://github.com/gridhead/metasource☆12Feb 16, 2026Updated 2 weeks ago
- Example project for the BRS-100-GW1NR9 FPGA development board.☆14Feb 14, 2026Updated 3 weeks ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- FDTD 3D simulator that generates s-parameters from OFF geometry files using one or more GPUs☆15Jan 16, 2023Updated 3 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Basic Common Modules☆46Dec 13, 2025Updated 2 months ago
- Learn NVDLA by SOMNIA☆42Dec 13, 2019Updated 6 years ago
- repo for CIS 371 Spring 2018☆15Apr 14, 2018Updated 7 years ago