A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for architecture research and education.
☆15Feb 10, 2026Updated 5 months ago
Alternatives and similar repositories for CacheSimulator
Users that are interested in CacheSimulator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago
- NoC simulation using gem5 (a simple tul)☆16Mar 23, 2024Updated 2 years ago
- Port of an unofficial EPFL LaTeX template to Typst.☆17Feb 25, 2025Updated last year
- A simplified cache simulator for instructional purposes☆15Dec 30, 2020Updated 5 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Archives of SystemC from The Ground Up Book Exercises☆35Nov 14, 2022Updated 3 years ago
- Software artifacts for "UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance" (…☆10Dec 27, 2021Updated 4 years ago
- Open-source textbook about CHERI capabilities, for a developer audience☆18Apr 16, 2026Updated 3 months ago
- HARV - HArdened Risc-V☆18Mar 10, 2022Updated 4 years ago
- Memory management is one of the most important parts of the operating system. KSM (Kernel Samepage Merging) in Linux kernel is a kind of…☆13Apr 8, 2018Updated 8 years ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 10 years ago
- ☆10Oct 8, 2021Updated 4 years ago
- The best rtl_uart in github! This is a UART design based on AXI Stream/Ready Vallid protocol. Support parameterized data bit width, clock…☆11May 8, 2025Updated last year
- A simulator of Cache☆85Aug 29, 2025Updated 10 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A transfer function widget implemented using ImGui☆19May 7, 2022Updated 4 years ago
- A simple MIPS Simulator that can simulate execution in MIPS for a small subset of instructions under several restrictions☆10Sep 10, 2019Updated 6 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Two Level Cache Controller implementation in Verilog HDL☆64Jul 9, 2020Updated 6 years ago
- A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog☆11Dec 26, 2020Updated 5 years ago
- A cycle accurate emulator for the 6502 microprocessor☆19Oct 1, 2023Updated 2 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- ☆22Oct 11, 2017Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Python Cache Hierarchy Simulator☆100Jul 29, 2025Updated 11 months ago
- Computer Architecture UIUC SP 2018☆15May 4, 2018Updated 8 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Updated this week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 10 months ago
- Linux kernel modules written in Rust☆31Nov 12, 2021Updated 4 years ago
- A branch predictor simulator in C++ that tests 6 different types of branch predictors.☆13Apr 26, 2018Updated 8 years ago
- yolog.dev releases, feedback & support☆16Feb 2, 2026Updated 5 months ago
- ☆13May 21, 2020Updated 6 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 基于树莓派3构建一个操作系统的系列教程☆13Jun 19, 2018Updated 8 years ago
- MATLAB Vision HDL☆16Jan 17, 2020Updated 6 years ago
- converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams☆17Nov 19, 2021Updated 4 years ago
- CPU Emulator for ARMv7☆14Jun 7, 2022Updated 4 years ago
- Research enablement kit for designing and prototyping a Cortex-M0–based SoC with custom IP integration (education, research)☆18Jun 13, 2025Updated last year
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆18Sep 17, 2013Updated 12 years ago
- https://pypi.python.org/pypi/Verilog_VCD☆22Mar 16, 2017Updated 9 years ago