Alternatives and similar repositories for matlab_visionhdl

Users that are interested in matlab_visionhdl are comparing it to the libraries listed below

• QuantumQuadrate / HamamatsuCameralink
  FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.
  ☆22Updated 9 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆21Updated last week
• benreynwar / fpga-sdrlib
  Verilog modules for software-defined radio.
  ☆18Updated 12 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆32Updated 5 years ago
• For-up / SEA-S7Guess
  SEA-S7_gesture recognition
  ☆17Updated 5 years ago
• txzing / modbus_crc_verilog
  FPGA纯逻辑实现modbus通信
  ☆22Updated 3 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆59Updated 3 years ago
• mcgodfrey / i2c-eeprom
  Controller for i2c EEPROM chip in Verilog for Mojo FPGA board
  ☆25Updated 9 years ago
• andrade824 / Verilog-SPI-Master
  A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen
  ☆19Updated 10 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆53Updated last week
• opalkelly-opensource / design-resources
  A collection of Opal Kelly provided design resources
  ☆17Updated last week
• lulinchen / face_detect_open
  A Voila-Jones face detector hardware implementation
  ☆33Updated 6 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆31Updated 4 years ago
• takeshineshiro / fpga_fibre_scan
  本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取…
  ☆29Updated 10 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆31Updated 5 years ago
• VideoGPU / FMC_MIPI
  FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface
  ☆19Updated 2 years ago
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆21Updated 6 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆46Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• ericgineer / CORDIC
  The CORDIC algorithm implemented in Octave/MATLAB and Verilog
  ☆32Updated 10 years ago
• esophagus-now / mpsoc_axidma
  A set of standalone kernel modules and userspace library for using the AXI DMA on a Zynq MPSoC
  ☆22Updated 5 years ago
• srimanthtenneti / SOC-Design-ARM-M0
  This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
  ☆12Updated 2 years ago
• absolutezero2730 / AXI_DMA_FIFO
  Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA
  ☆22Updated 6 years ago
• samsamfire / Kalman_Fpga
  Fixed Point Kalman filter for fpga
  ☆22Updated 5 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 4 years ago
• ptracton / UART_ECHO
  Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.
  ☆13Updated 10 years ago
• os-fpga / IP_Catalog
  IP Catalog for Raptor.
  ☆17Updated 11 months ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆34Updated 5 years ago
• GOOD-Stuff / srio_test
  Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)
  ☆18Updated 8 years ago