alexforencich / pin-uart

Related projects ⓘ

Alternatives and complementary repositories for pin-uart

• j-marjanovic / ocs-tray-mezzanine-adapter
  PCIe adapter for an FPGA accelerator for Open CloudServer
  ☆21Updated 4 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆39Updated 2 weeks ago
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆27Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• openXC7 / xc7k325t-blinky-nextpnr
  ☆43Updated last year
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆40Updated 7 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆52Updated last year
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• j-marjanovic / jtag-quartus-ft232h
  ☆44Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last month
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆36Updated 4 years ago
• antmicro / embench-tester
  ☆13Updated last year
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆55Updated 3 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆33Updated 5 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆27Updated 3 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• tow3rs / jtag-mpsse-blaster
  Use an MPSSE FTDI device as a JTAG interface in Quartus tools
  ☆14Updated 8 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• enjoy-digital / litesata_axiom
  ☆12Updated 3 years ago
• tomverbeure / bscan_tools
  Various JTAG boundary scan tools
  ☆33Updated 3 years ago
• olofk / observer
  ☆40Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 3 weeks ago
• uw-x / lora-modulator
  ☆19Updated last year
• enjoy-digital / litex-acorn-baseboard
  LiteX development baseboards arround the SQRL Acorn.
  ☆57Updated 7 months ago
• 360nosc0pe / scope
  Siglent SDS1x0xX-E FPGA bitstreams
  ☆40Updated last year
• hydrausb3 / wch-ch569-serdes
  WCH CH569 SerDes Reverse Engineering
  ☆25Updated 2 years ago