alexforencich / pin-uartLinks
FPGA board-level debugging and reverse-engineering tool
☆39Updated 2 years ago
Alternatives and similar repositories for pin-uart
Users that are interested in pin-uart are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- PCIe analyzer experiments☆63Updated 5 years ago
- LiteX development baseboards arround the SQRL Acorn.☆72Updated 9 months ago
- Small footprint and configurable SPI core☆46Updated last month
- PCIe adapter for an FPGA accelerator for Open CloudServer☆24Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆32Updated 3 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆57Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Small footprint and configurable JESD204B core☆50Updated 2 months ago
- VHDL PCIe Transceiver☆32Updated 5 years ago
- ☆54Updated 3 years ago
- ☆45Updated 3 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆100Updated last year
- USB Full Speed PHY☆48Updated 5 years ago
- ☆33Updated 3 years ago
- Open Source AES☆31Updated 3 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆38Updated 7 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- ☆17Updated 3 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated last year
- A configurable USB 2.0 device core☆32Updated 5 years ago
- ☆117Updated 2 years ago
- ☆16Updated last year
- Example projects for Quokka FPGA toolkit☆37Updated 3 years ago