Alternatives and similar repositories for cocotbext-uart

Users that are interested in cocotbext-uart are comparing it to the libraries listed below

• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆40Updated 5 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• schang412 / cocotbext-spi
  ☆28Updated last month
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 4 months ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆75Updated 5 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆70Updated 4 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• hypernyan / eth_vlg
  ☆78Updated 4 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆58Updated 6 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆65Updated 2 weeks ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆79Updated 3 years ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated last year
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆62Updated 3 months ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆40Updated 11 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆61Updated 3 weeks ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆47Updated 2 weeks ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆75Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated 2 months ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• alexforencich / cocotb-test
  Unit testing for cocotb
  ☆11Updated 2 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆44Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆33Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 9 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago