markos-stefanidis / FPGA-Based-HDR-algorithmLinks
Hardware implementation of HDR image producing algorithm
☆16Updated 3 years ago
Alternatives and similar repositories for FPGA-Based-HDR-algorithm
Users that are interested in FPGA-Based-HDR-algorithm are comparing it to the libraries listed below
Sorting:
- Bilinear interpolation realizes image scaling based on FPGA☆29Updated 5 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆63Updated 7 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆50Updated 5 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆36Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- 数字IC验证案例(SV and UVM)☆26Updated 4 years ago
- ☆38Updated 10 years ago
- AXI Interconnect☆55Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆39Updated 8 years ago
- UVM resource from github, run simulation use YASAsim flow☆32Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- image processing based FPGA☆116Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆39Updated 4 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- 异步FIFO的内部实现☆25Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- ☆28Updated 6 months ago
- ☆26Updated 4 years ago
- FIR implemention with Verilog☆50Updated 6 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制 器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Updated 6 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆17Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆58Updated 4 years ago
- AHB DMA 32 / 64 bits☆57Updated 11 years ago
- ARM中通过APB总线连接的UART模块☆71Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Updated 6 years ago
- UART design in SV and verification using UVM and SV☆52Updated 6 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Updated 5 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆28Updated 2 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago