Alternatives and similar repositories for FPGA-Based-HDR-algorithm

Users that are interested in FPGA-Based-HDR-algorithm are comparing it to the libraries listed below

• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• programer-guan / digital_ic_verification
  数字IC验证案例（SV and UVM）
  ☆26Updated 4 years ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆60Updated 6 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆47Updated 3 weeks ago
• muneeb-mbytes / uvm_tb_arch_doc_py
  A python project to automatically generate the UVM testbench document.
  ☆20Updated last year
• Noris4est / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆18Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆58Updated 8 years ago
• MaharshSuryawala / Image-Compression
  Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
  ☆16Updated 4 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆33Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆51Updated 3 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 11 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• Grootzz / Verilog-FIR
  FIR implemention with Verilog
  ☆48Updated 6 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• Lydaidai / The-car-base-on-FPGA
  开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…
  ☆14Updated 6 years ago
• JefferyLi0903 / MMC
  MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
  ☆22Updated 2 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆55Updated 2 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆48Updated 5 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆23Updated 5 years ago
• echoPinkApple / bilinear
  Bilinear interpolation realizes image scaling based on FPGA
  ☆27Updated 5 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆71Updated 5 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆66Updated 11 months ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆78Updated last year
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆66Updated 5 years ago