markos-stefanidis / FPGA-Based-HDR-algorithm
Hardware implementation of HDR image producing algorithm
☆15Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for FPGA-Based-HDR-algorithm
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植 )☆46Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 7 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆12Updated 4 years ago
- An AXI DDR3 SDRAM controller for FPGA☆23Updated 10 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- ☆16Updated 2 years ago
- ☆33Updated 2 years ago
- AXI Interconnect☆46Updated 3 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆14Updated 4 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- ☆34Updated 9 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆32Updated 7 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆17Updated 11 months ago
- 基于FPGA的三速以太网UDP协议栈设计☆18Updated 7 months ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- A 32 point radix-2 FFT module written in Verilog☆20Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆54Updated 3 months ago
- ☆9Updated 4 years ago
- ☆28Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- ARM中通过APB总线连接的UART模块☆59Updated 4 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆13Updated 2 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆18Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year