ZipCPU / vgasim
A Video display simulator
☆161Updated 6 months ago
Alternatives and similar repositories for vgasim:
Users that are interested in vgasim are comparing it to the libraries listed below
- Verilog wishbone components☆113Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆224Updated 4 years ago
- FuseSoC standard core library☆125Updated 2 weeks ago
- A simple, basic, formally verified UART controller☆287Updated last year
- A utility for Composing FPGA designs from Peripherals☆170Updated last month
- ☆128Updated 2 months ago
- A simple implementation of a UART modem in Verilog.☆118Updated 3 years ago
- ☆77Updated 11 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆142Updated this week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- SystemVerilog synthesis tool☆177Updated this week
- A full-speed device-side USB peripheral core written in Verilog.☆225Updated 2 years ago
- Naive Educational RISC V processor☆78Updated 4 months ago
- SoC based on VexRiscv and ICE40 UP5K☆152Updated 10 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆116Updated 8 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Example LED blinking project for your FPGA dev board of choice☆168Updated 2 months ago
- SpinalHDL Hardware Math Library☆83Updated 7 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆161Updated 11 months ago
- CoreScore☆143Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆141Updated 8 months ago
- VHDL library 4 FPGAs☆169Updated last week
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- Experimental flows using nextpnr for Xilinx devices☆225Updated 4 months ago
- A FPGA core for a simple SDRAM controller.☆117Updated 3 years ago
- Small footprint and configurable DRAM core☆390Updated last month
- VCD file (Value Change Dump) command line viewer☆113Updated 2 years ago