ZipCPU / sdr
A basic Soft(Gate)ware Defined Radio architecture
☆84Updated last year
Alternatives and similar repositories for sdr
Users that are interested in sdr are comparing it to the libraries listed below
Sorting:
- Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom☆105Updated 4 years ago
- PYNQ-Z1 + AD936X openwifi capable SDR platform☆89Updated 2 years ago
- ☆41Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆44Updated last year
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆72Updated 3 years ago
- Extensible FPGA control platform☆60Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆85Updated 2 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Updated 5 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆96Updated 8 years ago
- RTL implementation of components for DVB-S2☆117Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆36Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 4 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆113Updated 4 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆29Updated 2 years ago
- Small footprint and configurable JESD204B core☆42Updated 3 weeks ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆67Updated 3 years ago
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆54Updated last month
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆47Updated this week
- An RFSoC Frequency Planner developed using Python.☆27Updated last year
- LiteX Accelerator Block for GNU Radio☆24Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- HDL code for a DDS (direct digital synthesizer) with AXI stream interface☆18Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆88Updated 7 months ago
- Verilog digital signal processing components☆134Updated 2 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆76Updated 3 years ago
- LiteX based M2 SDR FPGA board.☆107Updated last week
- Python productivity for RFSoC platforms☆68Updated 11 months ago
- FPGA board-level debugging and reverse-engineering tool☆37Updated 2 years ago