ZipCPU / sdr
A basic Soft(Gate)ware Defined Radio architecture
☆71Updated 8 months ago
Related projects: ⓘ
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆39Updated 5 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆52Updated last week
- A collection of debugging busses developed and presented at zipcpu.com☆33Updated 8 months ago
- Small footprint and configurable JESD204B core☆39Updated 3 months ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆69Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆84Updated 4 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆102Updated 3 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆80Updated 7 years ago
- PYNQ-Z1 + AD936X openwifi capable SDR platform☆77Updated last year
- Extensible FPGA control platform☆52Updated last year
- ☆40Updated 6 months ago
- assorted library of utility cores for amaranth HDL☆77Updated this week
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆57Updated 3 weeks ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆75Updated last year
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆59Updated 2 years ago
- PicoRV☆43Updated 4 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆70Updated 2 years ago
- LiteX Accelerator Block for GNU Radio☆24Updated 2 years ago
- Virtual Development Board☆57Updated 2 years ago
- Bitstream relocation and manipulation tool.☆38Updated last year
- Digital FM Radio Receiver for FPGA☆57Updated 8 years ago
- A collection of phase locked loop (PLL) related projects☆95Updated 8 months ago
- Generate Zynq configurations without using the vendor GUI☆29Updated last year
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆48Updated 2 months ago
- Generic Logic Interfacing Project☆44Updated 4 years ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆64Updated 6 years ago
- FPGA board-level debugging and reverse-engineering tool☆28Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆28Updated this week
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago