将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。
☆28May 23, 2026Updated 5 months ago
Alternatives and similar repositories for verilog-design-skill
Users that are interested in verilog-design-skill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository defines a Claude Code skill for working with Verilog☆19Apr 21, 2026Updated 6 months ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- Agent skill for Verilog-2001 RTL generation and FPGA design workflows.☆332Aug 25, 2026Updated 2 months ago
- SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter☆14Mar 21, 2017Updated 9 years ago
- 全国大学生嵌入式芯片与系统设计竞赛（嵌赛FPGA）FPGA国赛决赛能力测试题（代码测试，考试），现有2019年、2020年、2023年、2024年、2025年的题目。有的是从CSDN上下的，不保证一定是。如果有人看到了，并有其他年份的题目，欢迎补充。☆93Dec 12, 2025Updated 11 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 8b10b Encoder/Decoder☆13Jul 17, 2014Updated 12 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆19Sep 21, 2025Updated last year
- Collection for agent skills on analog and mixed-signal (AMS) IC (integrated circuit) design☆35Jun 5, 2026Updated 5 months ago
- ☆19Aug 11, 2022Updated 4 years ago
- Artifacts for the "BBQ: A Fast and Scalable Integer Priority Queue for Hardware Packet Scheduling" paper that appears in NSDI '24.☆24Apr 23, 2024Updated 2 years ago
- ESnet general-purpose FPGA design library.☆14Nov 3, 2026Updated last week
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆16Dec 9, 2024Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Scalable FPGA General-Purpose Open-Source Toolchain☆113Mar 30, 2026Updated 7 months ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- Texture Tile Converter for Bitmaps☆10Mar 9, 2023Updated 3 years ago
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆34Aug 14, 2026Updated 2 months ago
- ☆13Oct 11, 2023Updated 3 years ago
- ☆11Aug 21, 2023Updated 3 years ago
- this repository is vim cfg for verilog.☆56Oct 17, 2026Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆24Updated this week
- ☆17Apr 7, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- LLM-Aided FPGA Design and Debug Flow☆43Aug 1, 2025Updated last year
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Developed an adaptive beamforming system using Kalman filter for DOA denoising and MUSIC algorithm for spatial filtering. Achieved better…☆16Mar 3, 2025Updated last year
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆41Aug 13, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆21Nov 10, 2017Updated 9 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆37Aug 7, 2021Updated 5 years ago
- ☆57Oct 12, 2026Updated last month
- 在FPGA中将图像数据输入到DDR3中，再输送到HDMI接口上进行显示。☆32Feb 5, 2023Updated 3 years ago
- 为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。☆28Oct 9, 2020Updated 6 years ago
- 12 agentic skills for analog IC design — architecture, sizing, verification, cross-model review, knowledge graph, and self-evolution. Wor…☆90Jul 2, 2026Updated 4 months ago
- Direct Access Memory for MPSoC☆13Updated this week
Are these results useful?