将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库,供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。
☆27May 23, 2026Updated 5 months ago
Alternatives and similar repositories for verilog-design-skill
Users that are interested in verilog-design-skill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository defines a Claude Code skill for working with Verilog☆19Apr 21, 2026Updated 6 months ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- Agent skill for Verilog-2001 RTL generation and FPGA design workflows.☆319Aug 25, 2026Updated last month
- 8b10b Encoder/Decoder☆13Jul 17, 2014Updated 12 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆19Sep 21, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- Artifacts for the "SurgeProtector: Mitigating Temporal Algorithmic Complexity Attacks using Adversarial Scheduling" paper that appears in…☆14Jun 24, 2022Updated 4 years ago
- ESnet general-purpose FPGA design library.☆14Oct 14, 2026Updated last week
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆16Dec 9, 2024Updated last year
- ☆54Oct 12, 2026Updated last week
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆32Aug 14, 2026Updated 2 months ago
- ☆14Jan 23, 2024Updated 2 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- In this report, we propose a filtering method combining Kalman and Wiener filter to remove noises from the video.☆11Sep 12, 2016Updated 10 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆23Oct 7, 2026Updated 2 weeks ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆33Feb 6, 2023Updated 3 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆37Aug 7, 2021Updated 5 years ago
- ☆17Apr 7, 2026Updated 6 months ago
- LLM-Aided FPGA Design and Debug Flow☆43Aug 1, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆20Nov 10, 2017Updated 8 years ago
- 在FPGA中将图像数据输入到DDR3中,再输送到HDMI接口上进行显示。☆32Feb 5, 2023Updated 3 years ago
- 为了学习UVM验证相关知识,需要动手尝试实际的项目。作为一个初学者,难以接触到实际的项目,于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中,挑选出一个简单的小设计,作为我的验证对象,并围绕它编写了UVM验证环境。☆28Oct 9, 2020Updated 6 years ago
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆41Aug 13, 2024Updated 2 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆19Oct 23, 2019Updated 7 years ago
- ☆26Feb 26, 2024Updated 2 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆24Apr 27, 2023Updated 3 years ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- Xilinx/AMD FPGA & MPSoC Vivado design skill for Claude — covers block design, IP config, XDC constraints, synthesis, implementation and b…☆477Apr 25, 2026Updated 5 months ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆25Dec 11, 2023Updated 2 years ago
- a Computing In Memory emULATOR framework☆16May 19, 2024Updated 2 years ago
- This is a campus navigation system, it was bulided by Qt.☆16May 28, 2022Updated 4 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago