FIR filter implementation
☆29Mar 19, 2020Updated 6 years ago
Alternatives and similar repositories for FIR_Implementation
Users that are interested in FIR_Implementation are comparing it to the libraries listed below
Sorting:
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 5 years ago
- A CIC filter implemented in Verilog☆25Sep 7, 2015Updated 10 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆48Oct 21, 2016Updated 9 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆32May 6, 2017Updated 8 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- ☆14Jun 30, 2019Updated 6 years ago
- PID controller☆25Jul 17, 2014Updated 11 years ago
- Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)☆31Aug 14, 2020Updated 5 years ago
- Delta Sigma DAC FPGA☆47Feb 21, 2025Updated last year
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog☆10Sep 26, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 3 months ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆74Jun 16, 2022Updated 3 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆34Aug 7, 2021Updated 4 years ago
- ☆24Jun 7, 2020Updated 5 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Aug 31, 2020Updated 5 years ago
- UESTC-雷达信号产生与处理的设计与验证☆19Jun 6, 2019Updated 6 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- ☆15May 9, 2020Updated 5 years ago
- A spiking neural network undergoes plastic changes based on the timing of neural spikes (MATLAB).☆10Feb 27, 2015Updated 11 years ago
- 基于 Ros2 Humble 的智能物流小车☆14Nov 4, 2023Updated 2 years ago
- Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) archit…☆17Jun 20, 2024Updated last year
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆63Jan 12, 2021Updated 5 years ago
- ☆12Jun 25, 2023Updated 2 years ago
- SDR design based on the AT86RF215 transceiver with IQ LVDS / FPGA DDR (dual-data-rate) interface☆22Jul 27, 2022Updated 3 years ago
- configurable cordic core in verilog☆53Jul 17, 2014Updated 11 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆30Mar 4, 2023Updated 3 years ago
- ☆14Sep 14, 2017Updated 8 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆76Mar 30, 2023Updated 2 years ago
- RDK X3 ROS2 Robot Car with Mecanum Wheel☆18Sep 26, 2025Updated 5 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆78Apr 11, 2022Updated 3 years ago
- 软件无线电，使用FPGA进行正交解调。☆23Feb 18, 2019Updated 7 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Nov 19, 2018Updated 7 years ago