benreynwar / fpga-sdrlib
Verilog modules for software-defined radio.
☆17Updated 11 years ago
Related projects ⓘ
Alternatives and complementary repositories for fpga-sdrlib
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- OscillatorIMP ecosystem FPGA IP sources☆25Updated 2 weeks ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆15Updated last year
- LMAC Core1 - Ethernet 1G/100M/10M☆16Updated last year
- WISHBONE Interconnect☆11Updated 7 years ago
- ☆13Updated last year
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 11 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Extensible FPGA control platform☆54Updated last year
- A collection of Opal Kelly provided design resources☆15Updated last month
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆29Updated 4 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- Imaging application using MIPI and DisplayPort to process image☆22Updated 4 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- The implementation of AD9371 on KC705☆20Updated 4 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 6 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆14Updated 3 months ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆16Updated 4 months ago
- APB Logic☆12Updated 9 months ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆15Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago