This repository defines a Claude Code skill for working with Verilog
☆19Apr 21, 2026Updated 6 months ago
Alternatives and similar repositories for claude-skill-verilog
Users that are interested in claude-skill-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库,供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆28May 23, 2026Updated 5 months ago
- An agent skill that turns an HDL / RTL / SoC architecture description into a clean SVG block diagram☆30Aug 10, 2026Updated 3 months ago
- Verilog Visualization: generate graph form verilog file and folder, support exporting to png, svg, html☆19Sep 30, 2026Updated last month
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- In this report, we propose a filtering method combining Kalman and Wiener filter to remove noises from the video.☆11Sep 12, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆11Aug 21, 2023Updated 3 years ago
- Developed an adaptive beamforming system using Kalman filter for DOA denoising and MUSIC algorithm for spatial filtering. Achieved better…☆16Mar 3, 2025Updated last year
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 6 months ago
- xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.☆10Oct 24, 2026Updated 2 weeks ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- hermes gateway platform for deltachat. With support for documents, voice messages, webxdc mini app generation and even voice calls.☆16Nov 5, 2026Updated last week
- ☆19Aug 11, 2022Updated 4 years ago
- Adaptive Decomposition and Extraction Network of Individual Fingerprint Features for Specific Emitter Identification☆13Aug 25, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆15Oct 7, 2026Updated last month
- Chisel RTL module of a unified ray tracer datapath pipeline. Supports ray-box intersection, ray-triangle intersection, acceleration for …☆15Jul 18, 2026Updated 3 months ago
- Various test models in WNNX format. It can view with `pip install wnetron && wnetron`☆12Jun 22, 2022Updated 4 years ago
- FPGA hardware design guide based on real-world projects. Covers SystemVerilog, Vivado workflow, timing closure, CDC handling, and Xilin…☆21Feb 6, 2026Updated 9 months ago
- Mindean is a lightweight, open-source mind map management platform.☆13Mar 14, 2026Updated 7 months ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- Time to Digital Converter on an FPGA☆18Oct 8, 2020Updated 6 years ago
- Airtl for VS Code: Vivado project hierarchy and block design viewer☆15Nov 3, 2026Updated last week
- 跨平台的 UESTC 教务系统(EAMS)成绩查询/监控工具:提供桌面 GUI(AvaloniaUI)与 云函数 两种使用方式,默认无头模式运行,并支持登录态保留与成绩更新通知(ntfy.sh)。☆19Jun 30, 2026Updated 4 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Note repository for studying Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL).☆16Feb 17, 2025Updated last year
- 轻量级跨平台 Verilog 仿真工程管理器,支持 Node cli 和 VS Code 扩展☆16Oct 16, 2026Updated 3 weeks ago
- The pixelated social network☆19Oct 20, 2026Updated 3 weeks ago
- Agent skill for Verilog-2001 RTL generation and FPGA design workflows.☆332Aug 25, 2026Updated 2 months ago
- DVSim is a build and run system written in Python that runs a variety of EDA tool flows☆16Updated this week
- Binary translation in Rust☆12Jun 22, 2020Updated 6 years ago
- A set of audio processing functions implemented by FPGA☆30Sep 28, 2021Updated 5 years ago
- Yank Note Extensions☆20Sep 19, 2026Updated last month
- A excellent markdown preview extension for vscode☆12Apr 2, 2026Updated 7 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆12Jul 13, 2023Updated 3 years ago
- ☆22Jul 1, 2024Updated 2 years ago
- BNG Image Format Implementation☆12Sep 19, 2020Updated 6 years ago
- 基于OpenCode 官方原版 ,内置运行时环境,解压即用。CJK中文修复 、Musl静态编译、适配旧GLIBC、适配旧版Windows和Linux操作系统。☆18Oct 28, 2026Updated 2 weeks ago
- DBT-RISE - A versatile Dynamic Binary Translation (DBT) based environment to implement instruction set simulator (ISS)☆12Updated this week
- Multi-class, Multi-kernel Relevance Vector Machine☆11Nov 12, 2011Updated 15 years ago
- Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP sp…☆27Jul 14, 2026Updated 3 months ago
Are these results useful?