YTYICer / AHB_SRAMLinks
This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.
☆14Updated 3 years ago
Alternatives and similar repositories for AHB_SRAM
Users that are interested in AHB_SRAM are comparing it to the libraries listed below
Sorting:
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆11Updated 3 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆96Updated 3 years ago
- AXI总线连接器☆103Updated 5 years ago
- 数字IC秋招项目、手撕代码☆38Updated last year
- 数字IC设计 学习笔记☆155Updated 3 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- 2023集创赛国二。基于脉动阵列写的一 个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆197Updated 10 months ago
- AMBA bus lecture material☆465Updated 5 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆179Updated 7 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆156Updated 4 years ago
- ☆19Updated 5 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆165Updated 2 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆44Updated 2 years ago
- AXI协议规范中文翻译版☆163Updated 3 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆206Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆130Updated 4 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆27Updated 2 years ago
- Radix-4 1024 point fft in verilog☆11Updated 5 years ago
- CPU Design Based on RISCV ISA☆122Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆187Updated last year
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆20Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆222Updated 2 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆57Updated last year
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆43Updated last year
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头,使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后,在使用FAST计算图像特征点的同时,构建滑动窗口计算图像各个像素点的BRIEF描述符,完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配,最后…☆14Updated 5 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆65Updated 6 years ago
- The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to rep…☆44Updated last year