Alternatives and similar repositories for fpga_decode_bitstream:

Users that are interested in fpga_decode_bitstream are comparing it to the libraries listed below

• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆53Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆67Updated 10 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆29Updated this week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆90Updated 2 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 9 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆51Updated 2 months ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆82Updated 10 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆57Updated last year
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆33Updated 3 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 3 months ago
• pulp-platform / redmule
  ☆42Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆70Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated 3 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆101Updated 8 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆113Updated 2 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆142Updated 3 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆29Updated 2 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆44Updated last month
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆87Updated 5 months ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆36Updated 10 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆90Updated this week