maxs-well / LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
☆39Updated 5 years ago
Alternatives and similar repositories for LMS-sound-filtering-by-Verilog
Users that are interested in LMS-sound-filtering-by-Verilog are comparing it to the libraries listed below
Sorting:
- LMS-Adaptive Filter implement using verilog and Matlab☆42Updated 8 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆15Updated 4 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- verilog☆21Updated last year
- FIR and LMS filter implementations in FPGAs☆13Updated 5 years ago
- FIR implemention with Verilog☆47Updated 5 years ago
- An AXI DDR3 SDRAM controller for FPGA☆36Updated last year
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆15Updated last year
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛 （高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。☆46Updated last year
- FIR filter implementation☆26Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- 基于FPGA的FFT☆16Updated 6 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21Updated last year
- Reed Solomon Encoder and Decoder Digital IP☆20Updated 4 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆59Updated 6 years ago
- 基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）☆48Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆63Updated 8 months ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- FPGA implementation of pose detection with Kalman filter. (verilog)☆36Updated 3 years ago
- 基于Verilog实现的全数字锁相环☆31Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago
- This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…☆43Updated 6 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆23Updated 2 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆17Updated 7 years ago
- SPI interface connect to APB BUS with Verilog HDL☆31Updated 3 years ago
- 帧差法运动目标检测，基于ZYNQ7020☆65Updated 3 years ago
- FPGA Technology Exchange Group相关文件管理☆44Updated last month
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- ☆10Updated 4 years ago