Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
☆307Aug 25, 2026Updated last month
Alternatives and similar repositories for verilog-generator
Users that are interested in verilog-generator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆30Aug 14, 2026Updated last month
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆27May 23, 2026Updated 4 months ago
- This repository defines a Claude Code skill for working with Verilog☆19Apr 21, 2026Updated 5 months ago
- Xilinx/AMD FPGA & MPSoC Vivado design skill for Claude — covers block design, IP config, XDC constraints, synthesis, implementation and b…☆461Apr 25, 2026Updated 5 months ago
- ☆178Sep 5, 2026Updated 3 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆51Aug 3, 2026Updated 2 months ago
- Vivado MCP Server — AI 驱动的 FPGA 开发助手，自动诊断 CRITICAL WARNING 并给出修复建议☆26Mar 12, 2026Updated 6 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 5 years ago
- ☆50Aug 20, 2026Updated last month
- Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP sp…☆24Jul 14, 2026Updated 2 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆140Apr 11, 2025Updated last year
- RTL agent team; Harness for Agentic hardware design and verificiation.☆53Aug 23, 2026Updated last month
- ☆30Jul 30, 2025Updated last year
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆19Dec 4, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Inference Engine for SiliconMind-V1 Verilog Coding Models☆52Jun 2, 2026Updated 4 months ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- Official Implementation of "Circuit Transformer: A Transformer That Preserves Logical Equivalence"☆28Mar 13, 2025Updated last year
- ☆15Jun 24, 2025Updated last year
- Digital HDL Design Full-stack Agents☆208Updated this week
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆40Nov 13, 2025Updated 10 months ago
- DeepGate3 for ICCAD2024☆14May 26, 2025Updated last year
- Analog HDL Design Full-stack Agents☆22Jun 8, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆30Jun 25, 2024Updated 2 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆45Sep 2, 2026Updated last month
- Implementation of Microscaling data formats in SystemVerilog.☆34Jul 6, 2025Updated last year
- Artifacts for the "SurgeProtector: Mitigating Temporal Algorithmic Complexity Attacks using Adversarial Scheduling" paper that appears in…☆13Jun 24, 2022Updated 4 years ago
- A curated, community-maintained list of ML/LLM research and tools for integrated-circuit design — across the full flow.☆26Aug 4, 2026Updated last month
- 小赵的数字系统综合设计代码仓库，欢迎参考☆13Nov 12, 2022Updated 3 years ago
- TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs [FPGA2026]☆39Mar 11, 2026Updated 6 months ago
- Scalable FPGA General-Purpose Open-Source Toolchain☆105Mar 30, 2026Updated 6 months ago
- 32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss dat…☆15Sep 15, 2026Updated 2 weeks ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 6 years ago
- ESnet general-purpose FPGA design library.☆14Sep 21, 2026Updated last week
- Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)☆12Feb 15, 2022Updated 4 years ago
- Pure FPGA implementation of music spectrum and waveform display, supporting background image loading from an SD card,FIR filtering-based …☆38Jan 24, 2025Updated last year
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆35Feb 24, 2026Updated 7 months ago
- Gowin USB3.0 Device Controller IP☆18Aug 20, 2024Updated 2 years ago
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year