Alternatives and similar repositories for renode-test-action

Users that are interested in renode-test-action are comparing it to the libraries listed below

• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 5 years ago
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆17Updated 3 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆41Updated last month
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆52Updated 3 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• antmicro / warp-pipe
  ☆16Updated last year
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆39Updated last week
• antmicro / zynq-mkbootimage
  An open source replacement of the Xilinx bootgen application.
  ☆115Updated last year
• olofk / observer
  ☆43Updated 5 years ago
• bavovanachte / sphinx-wavedrom
  A sphinx extension that allows including wavedrom diagrams by using its text-based representation
  ☆38Updated last year
• Gekkio / docker-fpga
  Dockerized FPGA toolchain experiments
  ☆29Updated last year
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆47Updated this week
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆102Updated last year
• polarfire-soc / icicle-kit-reference-design
  PolarFire SoC Icicle Kit Libero reference design
  ☆44Updated 3 weeks ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆55Updated last month
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 3 weeks ago
• QuickLogic-Corp / qorc-sdk
  Open source FreeRTOS SDK for EOS S3 MCU+eFPGA SoC including gateware, software and documentation under QuickLogic Open Reconfigurable Com…
  ☆50Updated 2 years ago
• nobodywasishere / vhdlref
  A usable language reference for VHDL that is concise, direct, and easy to understand.
  ☆26Updated 4 months ago
• blackmesalabs / sump3
  sump3 logic analyzer
  ☆37Updated last week
• antmicro / embench-tester
  ☆14Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆56Updated this week
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• lambdaconcept / lambdasoc
  ☆44Updated 10 months ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆72Updated 8 years ago
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆43Updated 5 years ago
• ernstblecha / vcd2tikztiming
  converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams
  ☆16Updated 4 years ago