alessandrocapotondi / mobilenet_v1_stmcube_ai
Mobilenet v1 (3,128,128, alpha=0.25) on STMH7 using STMCube AI
☆10Updated 5 years ago
Alternatives and similar repositories for mobilenet_v1_stmcube_ai:
Users that are interested in mobilenet_v1_stmcube_ai are comparing it to the libraries listed below
- Mobilenet v1 trained on Imagenet for STM32 using extended CMSIS-NN with INT-Q quantization support☆86Updated 4 years ago
- Nuclei Microcontroller Software Interface Standard Development Repo☆65Updated 3 months ago
- ☆21Updated 6 years ago
- ☆33Updated last year
- Make Baidu EdgeBoard Lite as a general Zynq FPGA development board☆24Updated last year
- A Voila-Jones face detector hardware implementation☆32Updated 6 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆28Updated last year
- ☆30Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆30Updated 4 years ago
- This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma dr…☆12Updated 6 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- Neural Engine, 16 input channels☆13Updated 2 years ago
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆67Updated last year
- Traffic-Sign-Reognition☆11Updated 4 years ago
- Computational Storage Device based on the open source project OpenSSD.☆20Updated 4 years ago
- Accelerating DNN inference and training on Zynq☆15Updated 4 years ago
- Driver stack (including user space libraries, kernel module and firmware) for the Arm® Ethos™-N NPU☆62Updated 3 months ago
- ☆24Updated 9 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Updated 3 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 4 years ago
- CMSIS DSP Library for PULPino microcontroller☆22Updated 6 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- INT-Q Extension of the CMSIS-NN library for ARM Cortex-M target☆18Updated 5 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆16Updated 6 months ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- OpenDLA for trying the demo and FPGA solution☆16Updated 2 years ago
- ☆78Updated last year
- Caffe to VHDL☆66Updated 4 years ago
- ☆11Updated last year
- JPEG图像压缩在STM32平台的实现,包含主要算法,但未创建文件信息部分,不是严格意义上的JPEG。☆16Updated 5 years ago