Alternatives and similar repositories for minnesota:

Users that are interested in minnesota are comparing it to the libraries listed below

• cfelton / gizflo
  that FPGA flow
  ☆9Updated 9 years ago
• andrecp / myhdl_simple_uart
  A very simple UART implementation in MyHDL
  ☆17Updated 10 years ago
• wware / myblaze
  MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…
  ☆17Updated 11 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆20Updated 9 years ago
• knielsen / ice40_viewer
  ☆59Updated last year
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• Cognoscan / VerilogCogs
  Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
  ☆20Updated 9 years ago
• jck / uhdl
  Utilities for MyHDL
  ☆18Updated last year
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 3 years ago
• daveshah1 / ulx3s
  ☆10Updated 6 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 2 months ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• mithro / pmod-hdmi
  HDMI Expansion Modules compatible with the Pmod standard
  ☆11Updated 6 years ago
• devbisme / myhdlpeek
  Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
  ☆40Updated last year
• mmicko / mikrobus-upduino
  Dual MikroBUS board for Upduino 2 FPGA
  ☆18Updated 6 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago
• pmezydlo / BeagleWire
  This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017
  ☆46Updated 6 years ago
• FPGAwars / toolchain-icestorm
  Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
  ☆38Updated 2 years ago
• RobertBaruch / n6800
  A 6800 CPU written in nMigen
  ☆49Updated 3 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆40Updated 11 months ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• mithro / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆17Updated 5 years ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated last month
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year