mattvenn / magic-inverterLinks
an inverter drawn in magic with makefile to simulate
☆26Updated 3 years ago
Alternatives and similar repositories for magic-inverter
Users that are interested in magic-inverter are comparing it to the libraries listed below
Sorting:
- PicoRV☆43Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Prefix tree adder space exploration library☆56Updated last year
- ☆38Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆99Updated last year
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆73Updated 4 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆31Updated last week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- An example of analogue design using open source IC design tools☆29Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- ☆38Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆35Updated 10 months ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- SAR ADC on tiny tapeout☆44Updated 11 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆85Updated 2 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- ☆71Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year
- A modern schematic entry and simulation program☆78Updated 2 weeks ago
- A set of rules and recommendations for analog and digital circuit designers.☆31Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated 3 weeks ago
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week