mattvenn / magic-inverter

Related projects: ⓘ

• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆34Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆28Updated 2 years ago
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year
• efabless / sky130_sram_macros_old
  ☆35Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆33Updated 8 months ago
• chili-chips-ba / openCologne
  Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chil…
  ☆37Updated this week
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆19Updated 2 years ago
• RTimothyEdwards / capiche
  Parasitic capacitance analysis of foundry metal stackups
  ☆10Updated 11 months ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆18Updated 6 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆45Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆34Updated last year
• b224hisl / rioschip
  ☆31Updated last year
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆40Updated last month
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆24Updated this week
• stineje / sky130RHBDlib
  ☆25Updated this week
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆31Updated 2 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆69Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆57Updated 2 years ago
• taneroksuz / fpu-sp
  IEEE 754 floating point library in system-verilog and vhdl
  ☆26Updated 4 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆27Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆34Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆34Updated 3 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 11 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆49Updated last year
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆17Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆40Updated 2 months ago