Alternatives and similar repositories for CW305-Arm-DesignStart

Users that are interested in CW305-Arm-DesignStart are comparing it to the libraries listed below

• socsecresearch / SoC_Vulnerability_Benchmarks
  ☆11Updated 8 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated last month
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆124Updated 2 weeks ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated 2 months ago
• ZSusskind / vcd2csv
  Extracts specified data from a VCD file into CSV form
  ☆10Updated 5 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 2 months ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆137Updated 3 years ago
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆48Updated 2 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 3 months ago
• antmicro / rowhammer-tester
  ☆71Updated last month
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• vmarribas / VerMFi
  VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …
  ☆20Updated 6 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆85Updated 2 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 9 months ago
• BLu85 / AES-GCM-128-192-256-bits
  Configurable AES-GCM IP (128, 192, 256 bits)
  ☆38Updated 4 months ago
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆33Updated 3 months ago
• ChairImpSec / PROLEAD
  PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software　　　　　　　　　　　　　FIESTA - Fault Injection Evaluation with Statistic…
  ☆41Updated last month
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 5 months ago
• SpinalHDL / VexRiscvSocSoftware
  ☆27Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆109Updated 2 weeks ago
• acmert / kyber-polmul-hw
  Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme
  ☆38Updated 3 years ago