schoeberl / risc-v-lab
Lab material for the three week course on builiding a RISC-V microprocessor
☆14Updated 4 months ago
Alternatives and similar repositories for risc-v-lab
Users that are interested in risc-v-lab are comparing it to the libraries listed below
Sorting:
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆23Updated 2 years ago
- ☆27Updated last month
- ☆33Updated last month
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated last week
- Open source process design kit for 28nm open process☆55Updated last year
- Simple UVM environment for experimenting with Verilator.☆20Updated 2 weeks ago
- A configurable SRAM generator☆48Updated 4 months ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- A tool for synthesizing Verilog programs☆78Updated this week
- A reference book on System-on-Chip Design☆27Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- The OpenPiton Platform☆16Updated 9 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆57Updated 3 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Advanced Architecture Labs with CVA6☆59Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- matrix-coprocessor for RISC-V☆14Updated 3 weeks ago
- ☆61Updated this week