AMDResearch / NPUEvalLinks
NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.
☆27Updated 3 months ago
Alternatives and similar repositories for NPUEval
Users that are interested in NPUEval are comparing it to the libraries listed below
Sorting:
- ☆37Updated last week
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Posit Arithmetic Cores generated with FloPoCo☆28Updated last year
- The Riallto Open Source Project from AMD☆84Updated 10 months ago
- ☆12Updated 9 months ago
- Example for running IREE in a bare-metal Arm environment.☆40Updated 6 months ago
- LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs☆17Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆48Updated 3 weeks ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last month
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated this week
- ☆62Updated this week
- ☆123Updated this week
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆57Updated this week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆37Updated last week
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated last month
- A stream to RTL compiler based on MLIR and CIRCT☆16Updated 3 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Updated last year
- PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow☆69Updated 2 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Updated 3 years ago
- ☆29Updated 8 years ago
- CGRA framework with vectorization support.☆43Updated last week
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 6 years ago
- BLAS implementation for Intel FPGA☆78Updated 5 years ago
- ☆60Updated 2 years ago