NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.
☆32Nov 8, 2025Updated 8 months ago
Alternatives and similar repositories for NPUEval
Users that are interested in NPUEval are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Riallto Open Source Project from AMD☆86Apr 10, 2025Updated last year
- Ryzen AI Dockerfiles for ML, Robotics and Development Environments☆80Jul 9, 2026Updated last week
- Reconfigurable Stream Network Architecture☆18May 8, 2025Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆27May 18, 2025Updated last year
- Light Cube using PYNQ☆10Aug 4, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆63Mar 8, 2026Updated 4 months ago
- Fork of LLVM to support AMD AIEngine processors☆204Updated this week
- ☆29Feb 21, 2018Updated 8 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆20Dec 29, 2024Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆37Mar 12, 2026Updated 4 months ago
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 9 years ago
- PYNQ Composabe Overlays☆79Jun 17, 2024Updated 2 years ago
- Networking Overlay on PYNQ☆51Mar 5, 2019Updated 7 years ago
- ☆14Aug 14, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆19Sep 15, 2021Updated 4 years ago
- An MLIR-based toolchain for AMD AI Engine-enabled devices.☆667Updated this week
- PYNQ-ZU, AUP UltraScale+ MPSoC academic board☆29Oct 6, 2025Updated 9 months ago
- AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration (SC25)☆24Apr 14, 2026Updated 3 months ago
- ☆17May 25, 2026Updated last month
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Aug 5, 2022Updated 3 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆120Jan 28, 2026Updated 5 months ago
- A compiler for lowering quantized ML models to AMD AI Engine (AIE) firmware.☆20Updated this week
- Python productivity for RFSoC platforms☆97Jul 3, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AMD XDNA Driver (amdxdna.ko) for Linux and XRT SHIM library☆605Updated this week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆174Mar 12, 2026Updated 4 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆75Jul 1, 2026Updated 3 weeks ago
- pynq framework for antsdr☆37May 31, 2024Updated 2 years ago
- ☆14Jan 24, 2023Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆30Jul 7, 2026Updated 2 weeks ago
- ☆12Apr 7, 2020Updated 6 years ago
- AI Accelerators-SC23-tutorial Repository☆12Nov 12, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆62Nov 23, 2021Updated 4 years ago
- llama.cpp fork with AMD XDNA2 NPU backend for Ryzen AI MAX (npu5/XDNA2) — matrix multiply offload via XRT☆19Apr 1, 2026Updated 3 months ago
- Board files to build Ultra 96 PYNQ image☆159Sep 14, 2025Updated 10 months ago
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆18Updated this week
- ☆10May 20, 2022Updated 4 years ago
- ☆14Nov 15, 2024Updated last year
- DPU on PYNQ☆248Aug 12, 2025Updated 11 months ago