Xilinx / xup_aie_training
Hands-on experience programming AI Engines using Vitis Unified Software Platform
☆36Updated last month
Related projects: ⓘ
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆81Updated last month
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆77Updated last month
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆28Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture☆119Updated last month
- ☆56Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆60Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆62Updated last month
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆53Updated this week
- ☆23Updated 5 months ago
- ☆23Updated 3 years ago
- ☆28Updated 2 weeks ago
- RapidStream-TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆149Updated last week
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆62Updated 5 years ago
- Public repostory for the DAC 2021 paper "Scaling up HBM Efficiency of Top-K SpMV forApproximate Embedding Similarity on FPGAs"☆14Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- ☆31Updated 3 years ago
- ☆86Updated 6 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆48Updated 2 years ago
- ☆27Updated 5 years ago
- ☆33Updated 6 months ago
- EQueue Dialect☆38Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆73Updated last year
- FPGA version of Rodinia in HLS C/C++☆32Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆58Updated 9 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆41Updated 3 months ago
- cycle accurate Network-on-Chip Simulator☆24Updated last year
- Processing in Memory Emulation☆18Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆56Updated 2 years ago
- CGRA framework with vectorization support.☆18Updated 5 months ago
- ☆27Updated 5 years ago