Xilinx / HPCG_FPGALinks
☆9Updated 3 years ago
Alternatives and similar repositories for HPCG_FPGA
Users that are interested in HPCG_FPGA are comparing it to the libraries listed below
Sorting:
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- ☆33Updated 10 months ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated this week
- DASS HLS Compiler☆29Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 11 months ago
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 2 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated 2 months ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated last year
- ☆30Updated 6 years ago
- matrix-coprocessor for RISC-V☆19Updated 3 months ago
- ☆86Updated last year
- ☆58Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last month
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆59Updated this week
- Next generation CGRA generator☆112Updated this week
- ☆71Updated this week
- FPGA version of Rodinia in HLS C/C++☆38Updated 4 years ago
- ☆25Updated 4 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆15Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago