Xilinx / HPCG_FPGA
☆9Updated 2 years ago
Alternatives and similar repositories for HPCG_FPGA:
Users that are interested in HPCG_FPGA are comparing it to the libraries listed below
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆18Updated last year
- A polyhedral compiler for hardware accelerators☆56Updated 7 months ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆20Updated last week
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated 10 months ago
- Tutorial Material from the SST Team☆19Updated 10 months ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 3 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 6 months ago
- A OpenCL-based FPGA benchmark suite for HPC☆32Updated last month
- AI Accelerators-SC23-tutorial Repository☆11Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆35Updated 4 years ago
- ☆33Updated 6 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- CGRA framework with vectorization support.☆27Updated this week
- ☆27Updated 5 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆28Updated 5 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆46Updated 7 months ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- ☆17Updated this week
- ☆57Updated last year
- ☆87Updated last year