Alternatives and similar repositories for OpenMDS

Users that are interested in OpenMDS are comparing it to the libraries listed below

• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 5 years ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆25Updated 6 months ago
• hplp / PiMulator
  Processing in Memory Emulation
  ☆22Updated 2 years ago
• CMU-SAFARI / Sectored-DRAM
  A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…
  ☆12Updated last year
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆71Updated 2 years ago
• he-actlab / planaria.code
  ☆29Updated 4 years ago
• Xilinx / SLASH
  A research shell for Alveo V80
  ☆19Updated last month
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆19Updated 7 months ago
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• ucb-bar / MoCA
  ☆28Updated 2 years ago
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆55Updated 4 years ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆21Updated 8 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• arkhadem / DX100
  Artifact for "DX100: A Programmable Data Access Accelerator for Indirection (ISCA 2025)" paper
  ☆13Updated last month
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆72Updated 8 months ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• PolyArch / gem-forge-framework
  ☆26Updated 2 years ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆15Updated last year
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆45Updated 8 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• diwu1990 / UnarySim
  This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…
  ☆45Updated 4 months ago
• miglopst / PIM_NDP_papers
  ☆69Updated 4 years ago
• hpc-ulisboa / NDPmulator
  A Full-System Framework for Simulating NDP devices from Caches to DRAM
  ☆20Updated last year
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆84Updated 6 years ago
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆23Updated 7 years ago