Xilinx / GO-PYNQLinks
Xilinx Contest Kshitij 2019
☆19Updated 2 years ago
Alternatives and similar repositories for GO-PYNQ
Users that are interested in GO-PYNQ are comparing it to the libraries listed below
Sorting:
- Adding PR to the PYNQ Overlay☆17Updated 8 years ago
- HOG + SVM on FPGA☆26Updated 4 years ago
- ☆29Updated 7 years ago
- Networking Overlay on PYNQ☆49Updated 6 years ago
- Xilinx Deep Learning IP☆92Updated 4 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 7 years ago
- ☆84Updated 4 years ago
- Design contest for DAC 2018☆17Updated 7 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- ☆44Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.☆14Updated 7 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆105Updated 7 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- PYNQ, Neural network Language model, Overlay☆107Updated 6 years ago
- ☆58Updated 5 years ago
- PYNQ demo as seen at FPL 2018☆21Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- A multi-board Extended Kalman Filter (EKF)☆32Updated 6 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 7 years ago
- Caffe to VHDL☆67Updated 5 years ago
- The Demo that was presented at FCCM.☆15Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆15Updated 8 years ago
- A real time Histogram of Oriented Gradients Implementation on FPGA☆32Updated 6 years ago