Xilinx / RFNoC-HLS-NeuralNetLinks
☆108Updated 6 years ago
Alternatives and similar repositories for RFNoC-HLS-NeuralNet
Users that are interested in RFNoC-HLS-NeuralNet are comparing it to the libraries listed below
Sorting:
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆154Updated 5 years ago
- Caffe to VHDL☆67Updated 5 years ago
- PYNQ, Neural network Language model, Overlay☆108Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆106Updated 7 years ago
- Board files to build Ultra 96 PYNQ image☆156Updated 7 months ago
- Xilinx Deep Learning IP☆92Updated 4 years ago
- PYNQ Composabe Overlays☆73Updated last year
- ☆84Updated 5 years ago
- A convolutional neural network implemented in hardware (verilog)☆159Updated 7 years ago
- RISC-V Integration for PYNQ☆174Updated 6 years ago
- ☆29Updated 7 years ago
- DPU on PYNQ☆225Updated last year
- Avnet Board Definition Files☆134Updated last week
- ☆118Updated 4 years ago
- Vitis HLS Library for FINN☆204Updated last week
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆111Updated 5 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆105Updated 2 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆276Updated 5 years ago
- ☆90Updated 5 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 3 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 5 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- Computer Vision Overlays on Pynq☆179Updated 5 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆102Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆103Updated 7 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆87Updated 2 months ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago