A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.
☆11Jan 21, 2018Updated 8 years ago
Alternatives and similar repositories for model-ghdl
Users that are interested in model-ghdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 6 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- VHDLproc is a VHDL preprocessor☆25May 12, 2022Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆70Feb 16, 2026Updated 8 months ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- cryptography ip-cores in vhdl / verilog☆43Feb 20, 2021Updated 5 years ago
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated 5 months ago
- Python library for operations with VCD and other digital wave files☆55May 19, 2026Updated 5 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.☆12Jul 7, 2026Updated 3 months ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 6 years ago
- Streaming based VHDL parser.☆86Updated this week
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- Initial 0.0.1 push☆13Jun 10, 2016Updated 10 years ago
- Cross EDA Abstraction and Automation☆45Updated this week
- VHDL related news.☆27Updated this week
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- VHDL plugin for RgGen☆15Jul 1, 2026Updated 4 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Unified Coverage Interoperability Standard (UCIS)☆15Updated this week
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 6 months ago
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 10 months ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- Network protocol libraries for VHDL test benches☆14Mar 9, 2026Updated 7 months ago
- vhdl related contents☆11Apr 27, 2020Updated 6 years ago
- Interfacing VHDL and foreign languages with VUnit☆16Feb 20, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- GUI editor for hardware description designs☆30Sep 14, 2026Updated last month
- RIFFA (Reusable Integration Framework for FPGA Accelerators) is a framework developed in University of California, San Diego. This projec…☆14Jul 16, 2015Updated 11 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆49Feb 12, 2026Updated 8 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆39Dec 24, 2020Updated 5 years ago
- OSVVM Ethernet Library☆10Oct 9, 2026Updated 3 weeks ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago