umarcor / hwstudio
GUI editor for hardware description designs
☆27Updated last year
Related projects ⓘ
Alternatives and complementary repositories for hwstudio
- sample VCD files☆36Updated 9 months ago
- ☆12Updated 2 years ago
- Wishbone interconnect utilities☆37Updated 6 months ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Atom Hardware IDE☆13Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 11 months ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆14Updated 8 months ago
- USB virtual model in C++ for Verilog☆28Updated last month
- Library of reusable VHDL components☆25Updated 8 months ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- VHDL plugin for RgGen☆11Updated this week
- ☆20Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- A padring generator for ASICs☆22Updated last year
- VHDL Code for infrastructural blocks (designed for FPGA)☆13Updated 2 years ago
- ☆29Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆29Updated this week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- Virtual development board for HDL design☆39Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆39Updated 3 years ago
- Generate symbols from HDL components/modules☆20Updated last year
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago