umarcor / hwstudioLinks
GUI editor for hardware description designs
☆28Updated last year
Alternatives and similar repositories for hwstudio
Users that are interested in hwstudio are comparing it to the libraries listed below
Sorting:
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Updated 2 years ago
- ☆14Updated 3 years ago
- sample VCD files☆37Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated 3 weeks ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆21Updated 3 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 5 years ago
- Library of reusable VHDL components☆28Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated this week
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- ☆20Updated 3 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆30Updated 4 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- VHDL plugin for RgGen☆12Updated 3 weeks ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆22Updated this week
- ☆34Updated 4 years ago
- ☆32Updated 2 years ago