GMUCERG / LWC

Related projects ⓘ

Alternatives and complementary repositories for LWC

• IAIK / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated last month
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆15Updated 8 months ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆34Updated 3 years ago
• aneeshkandi14 / ascon-hw-public
  ☆15Updated 4 months ago
• rprimas / ascon-verilog
  Verilog Hardware Design of Ascon v1.2
  ☆19Updated this week
• Chair-for-Security-Engineering / SILVER
  SILVER - Statistical Independence and Leakage Verification
  ☆12Updated last year
• ascon / ascon-hardware
  NIST LWC Hardware Reference Implementation of Ascon v1.2
  ☆24Updated last year
• Chair-for-Security-Engineering / VERICA
  ☆12Updated last month
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆41Updated last year
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆27Updated 8 months ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆45Updated 4 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆25Updated 2 years ago
• xiang-rc / cfntt_ref
  ☆24Updated 3 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆75Updated this week
• flokrieger / Aloha-HE
  ☆13Updated 2 months ago
• Ko- / riscvcrypto
  Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture
  ☆31Updated 4 years ago
• ChairImpSec / PROLEAD
  PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software
  ☆32Updated this week
• intel / hexl-fpga
  Intel Homomorphic Encryption Acceleration Library for FPGAs, including open source implementation of FPGA kernels for accelerating NTT, I…
  ☆94Updated last year
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆42Updated 3 weeks ago
• coruus / canright-aes-sboxes
  David Canright's tiny AES S-boxes
  ☆21Updated 10 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆33Updated last year
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆29Updated last month
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆31Updated 7 years ago
• acmert / kyber-polmul-hw
  Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme
  ☆25Updated 2 years ago
• KULeuven-COSIC / HEAT
  Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)
  ☆55Updated 4 years ago
• Secure-Embedded-Systems / Masked-AES-Implementation
  ☆21Updated 4 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆91Updated last year
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆17Updated 4 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆61Updated 5 years ago
• Chair-for-Security-Engineering / AGEMA
  Automated Generation of Masked Hardware
  ☆16Updated 6 months ago