Alternatives and similar repositories for list_of_Xilinx_FPGAs

Users that are interested in list_of_Xilinx_FPGAs are comparing it to the libraries listed below

• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last month
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆29Updated 5 months ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• rriggs / kintex-7-hpc-v2-board-files
  Vivado board files for the Kintex 7 HPC V2 FPGA board.
  ☆26Updated 5 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 10 months ago
• slaclab / axi-pcie-core
  ☆23Updated last week
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated last week
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆19Updated 9 years ago
• pulp-platform / ELAU
  ☆19Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆65Updated 9 months ago
• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆17Updated 9 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆18Updated 6 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 3 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆51Updated this week
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆31Updated 2 weeks ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month