☆41Mar 29, 2026Updated 2 months ago
Alternatives and similar repositories for list_of_Xilinx_FPGAs
Users that are interested in list_of_Xilinx_FPGAs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 4 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆20Jul 9, 2024Updated last year
- 3D FPGA Architecture Exploration Tool☆19Feb 24, 2026Updated 3 months ago
- A OpenCL-based FPGA benchmark suite for HPC☆37May 4, 2026Updated last month
- Unified Coverage Interoperability Standard (UCIS)☆14Jan 28, 2026Updated 4 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆22Oct 31, 2024Updated last year
- A fork of https://ixo-jtag.sourceforge.net/ with a CPLD design fix☆16Jul 27, 2024Updated last year
- Tiny Tapeout 06☆16Nov 15, 2025Updated 7 months ago
- A research shell for Alveo V80☆40Updated this week
- Hog (HDL-on-git) is an open-source tool to manage FPGA projects on git☆53Updated this week
- ☆20May 25, 2026Updated 3 weeks ago
- ☆13Apr 15, 2025Updated last year
- A VHDL implementation of an AXI4 Master☆16Nov 7, 2017Updated 8 years ago
- Xilinx 14.7 patch for Win10 32/64☆31Jan 28, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Logic circuit analysis and optimization☆50Feb 2, 2026Updated 4 months ago
- Rocq framework to define the semantics of CPU architectures☆37Updated this week
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 3 years ago
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆66Jun 11, 2026Updated last week
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆25Jan 27, 2023Updated 3 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Nov 29, 2024Updated last year
- Raspberry Pi Pico example interface code with E-Paper Display 1.54 inch from Waveshare.com.☆15Sep 22, 2024Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆41Oct 3, 2023Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆27May 18, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…☆21Jul 11, 2016Updated 9 years ago
- ☆21Jun 9, 2026Updated last week
- Facilitates building open source tools for working with hardware description languages (HDLs)☆68Dec 4, 2019Updated 6 years ago
- Sum-Product Network learning routines in python☆27Jun 10, 2015Updated 11 years ago
- Template Repository for Xilinx HLS design flow☆12Nov 18, 2021Updated 4 years ago
- A flexible and scalable development platform for modern FPGA projects.☆44Updated this week
- A small 32-bit implementation of the RISC-V architecture☆33Apr 10, 2026Updated 2 months ago
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- Re-coded Xilinx primitives for Verilator use☆54Jun 24, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A RRAM addon for the NCSU FreePDK 45nm☆26Jan 10, 2022Updated 4 years ago
- TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.☆56Jun 7, 2026Updated last week
- Repository for an article called "Fast MiniMax Polynomial Approximations of Sine and Cosine"☆13Mar 8, 2019Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- MulApprox - A comprehensive library of state-of-the-art approximate multipliers☆34Jun 27, 2021Updated 4 years ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆71Nov 21, 2021Updated 4 years ago
- A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.☆81Updated this week