Alternatives and similar repositories for list_of_Xilinx_FPGAs

Users that are interested in list_of_Xilinx_FPGAs are comparing it to the libraries listed below

• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 3 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆30Updated 9 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆32Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆64Updated this week
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• b224hisl / rioschip
  ☆33Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 4 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• siliconcompiler / lambdalib
  Hardware abstraction library
  ☆43Updated this week
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆44Updated 11 months ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆75Updated last month
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 7 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆32Updated 5 years ago