Alternatives and similar repositories for list_of_Xilinx_FPGAs:

Users that are interested in list_of_Xilinx_FPGAs are comparing it to the libraries listed below

• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆30Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆17Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆29Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• rriggs / kintex-7-hpc-v2-board-files
  Vivado board files for the Kintex 7 HPC V2 FPGA board.
  ☆26Updated 4 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 3 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated 2 months ago
• merledu / TileLink
  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
  ☆20Updated 4 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆35Updated 11 months ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆32Updated 4 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆41Updated last month
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆25Updated 9 months ago
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 7 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆19Updated 2 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆21Updated last month
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 6 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆26Updated 8 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆50Updated last month
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆32Updated this week
• The-OpenROAD-Project / megaboom
  ☆24Updated this week