Alternatives and similar repositories for list_of_Xilinx_FPGAs:

Users that are interested in list_of_Xilinx_FPGAs are comparing it to the libraries listed below

• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆17Updated 2 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆27Updated 11 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated 2 weeks ago
• merledu / TileLink
  TileLink Uncached Lightweight (TL-UL) implementation on Chisel.
  ☆20Updated 4 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆24Updated 2 weeks ago
• waviousllc / wav-slink-hw
  An Open Source Link Protocol and Controller
  ☆26Updated 3 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 5 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• pulp-platform / axi_llc
  ☆25Updated this week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated last year
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆22Updated last week
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆30Updated 10 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆37Updated last week
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆31Updated last month
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆32Updated last year
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆48Updated 2 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated last year