mnmhdanas / DA-Based-LMS-Adaptive-filter
Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .
☆15Updated 3 years ago
Alternatives and similar repositories for DA-Based-LMS-Adaptive-filter:
Users that are interested in DA-Based-LMS-Adaptive-filter are comparing it to the libraries listed below
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Updated 9 years ago
- FIR band-pass filter using Verilog HDL.☆11Updated 4 years ago
- FIR Filter in Verilog☆13Updated 5 years ago
- Router 1 x 3 verilog implementation☆13Updated 3 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆23Updated 2 years ago
- Reed Solomon Encoder and Decoder Digital IP☆19Updated 4 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆14Updated 4 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Updated 5 years ago
- FIR，FFT based on Verilog☆13Updated 7 years ago
- CORDIC VLSI-IP for deep learning activation functions☆14Updated 5 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆29Updated 3 years ago
- FIR implemention with Verilog☆47Updated 5 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆42Updated 8 years ago
- LMS sound filtering by Verilog☆39Updated 5 years ago
- SPI Master Core clone from OpenCores☆11Updated 11 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- An 8 input interrupt controller written in Verilog.☆26Updated 13 years ago
- Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic☆31Updated 8 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 5 years ago
- Wi-Fi LDPC codec Verilog IP core☆17Updated 5 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆32Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆16Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆56Updated 2 years ago
- Integration of SIFT and LES Algorithms☆12Updated last year
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Updated 6 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆15Updated 3 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago