Hardware Viterbi Decoder in verilog
☆32May 28, 2019Updated 7 years ago
Alternatives and similar repositories for viterbi_decoder
Users that are interested in viterbi_decoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆64Mar 15, 2024Updated 2 years ago
- An 8 input interrupt controller written in Verilog.☆30Mar 22, 2012Updated 14 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 4 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Polar Codes Implementation on Vhdl☆13Jun 4, 2016Updated 10 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 7 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆38Jan 10, 2019Updated 7 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆14Aug 12, 2020Updated 5 years ago
- ☆10Apr 28, 2023Updated 3 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- An implementation of the decoding of BCH codes resistant to timing attacks☆11Sep 18, 2020Updated 5 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Video Stream Scaler☆42Jul 17, 2014Updated 12 years ago
- Many peripherals in Verilog ready to use☆41Dec 29, 2024Updated last year
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- 16 bit CPU created in Vivado with Verilog☆22Jun 30, 2022Updated 4 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- Cobra-W -> Cobra-RE 将进一步提升漏洞发现的准确性并降低漏报率（弃坑了）☆16Aug 15, 2020Updated 5 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 13 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆14Dec 16, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆10May 24, 2021Updated 5 years ago
- This application estimate iterative decoding threshold using degree description, Stephan ten Brink. More general decription of LDPC codes…☆13Apr 28, 2023Updated 3 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 8 months ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- LUT LDPC is a collection of software tools to design and test LDPC decoders based on discrete message passing decoding using lookup table…☆17May 30, 2018Updated 8 years ago
- Polar coding, decoding, and testing☆13Oct 11, 2023Updated 2 years ago
- A list Viterbo algorithm for decoding PAC codes with various code constructions/rate-profiles☆11May 6, 2022Updated 4 years ago
- A Python 3 C++ extension to simplify development using USRP software-defined radios.☆12Mar 16, 2026Updated 4 months ago
- ☆16Mar 27, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Feb 26, 2021Updated 5 years ago
- The FPGA design for the FreeSRP's Artix 7 FPGA☆25Apr 12, 2017Updated 9 years ago
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆10Sep 30, 2020Updated 5 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago