Hardware Viterbi Decoder in verilog
☆31May 28, 2019Updated 7 years ago
Alternatives and similar repositories for viterbi_decoder
Users that are interested in viterbi_decoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆63Mar 15, 2024Updated 2 years ago
- elementary LDPC codes, density evolution and exit analysis☆11Jan 27, 2022Updated 4 years ago
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- Polar Codes Implementation on Vhdl☆13Jun 4, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LUT LDPC is a collection of software tools to design and test LDPC decoders based on discrete message passing decoding using lookup table…☆18May 30, 2018Updated 8 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Aug 26, 2021Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆41May 10, 2019Updated 7 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆17Aug 21, 2018Updated 8 years ago
- Algebraic methods for construction QC-LDPC and cyclic LDPC LDGM EG-LDPC source codes☆20Dec 1, 2024Updated last year
- Importance Sampling and Linear Programming based Enumerating and Weighing of Trapping sets in LDPC codes, ISING models and related DNN A…☆23Jul 31, 2025Updated last year
- Simple implementation (polynomial approx.) of Protograph EXIT-chart (PEXIT) for estimation of iterative decoding threshold of LDPC codes …☆24Jul 19, 2025Updated last year
- This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsin…☆11Nov 16, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Solution to COA LAB Assgn, IIT Kharagpur☆38Jan 10, 2019Updated 7 years ago
- Simulated annealing lifting for high girth QC-LDPC include ACE/EMD optimization. Make QC-LDPC from protograph (base matrix)☆29May 31, 2024Updated 2 years ago
- ☆10Apr 28, 2023Updated 3 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆11May 24, 2021Updated 5 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆160Jul 17, 2022Updated 4 years ago
- Cobra-W -> Cobra-RE 将进一步提升漏洞发现的准确性并降低漏报率(弃坑了)☆16Aug 15, 2020Updated 6 years ago
- The Repository contains the code of various Digital Circuits☆14Aug 7, 2023Updated 3 years ago
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 12 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆15Dec 16, 2020Updated 5 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 9 years ago
- ☆12Sep 22, 2021Updated 5 years ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆253Nov 29, 2023Updated 2 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- An implementation of the decoding of BCH codes resistant to timing attacks☆11Sep 18, 2020Updated 6 years ago
- Video Stream Scaler☆43Jul 17, 2014Updated 12 years ago
- Polar coding, decoding, and testing☆13Oct 11, 2023Updated 3 years ago
- A PyTorch-based numerical simulator for decoders in quantum error correction.☆15Oct 19, 2026Updated 2 weeks ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- 16 bit CPU created in Vivado with Verilog☆23Jun 30, 2022Updated 4 years ago
- ☆10Aug 12, 2021Updated 5 years ago
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆50Jul 18, 2020Updated 6 years ago
- ☆10Oct 14, 2019Updated 7 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- A Python 3 C++ extension to simplify development using USRP software-defined radios.☆12Mar 16, 2026Updated 7 months ago