coole198669 / viterbi_decoderLinks
Hardware Viterbi Decoder in verilog
☆26Updated 6 years ago
Alternatives and similar repositories for viterbi_decoder
Users that are interested in viterbi_decoder are comparing it to the libraries listed below
Sorting:
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆56Updated 3 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆151Updated 4 months ago
- Verilog based BCH encoder/decoder☆122Updated 2 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Gigabit Ethernet UDP communication driver☆77Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- ☆69Updated 3 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- SPI interface connect to APB BUS with Verilog HDL☆34Updated 4 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆131Updated last year
- AXI4 BFM in Verilog☆32Updated 8 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- ☆36Updated 9 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Updated 11 years ago
- AXI Interconnect☆50Updated 3 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆51Updated 7 years ago
- verilog☆21Updated 2 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆31Updated 5 years ago
- ☆72Updated 3 years ago
- use Verilog HDL implemente bicubic interpolation in FPGA☆24Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- 10G Low Latency Ethernet☆56Updated 2 years ago