Hardware Viterbi Decoder in verilog
☆31May 28, 2019Updated 6 years ago
Alternatives and similar repositories for viterbi_decoder
Users that are interested in viterbi_decoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆61Mar 15, 2024Updated 2 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆22Jul 7, 2024Updated last year
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆13Jul 28, 2021Updated 4 years ago
- Polar Codes Implementation on Vhdl☆14Jun 4, 2016Updated 9 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆18Aug 21, 2018Updated 7 years ago
- A MATLAB function library containing encoders, decoders and weight enumerators for Reed-Muller codes.☆11Aug 19, 2023Updated 2 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆37Jan 10, 2019Updated 7 years ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆225Nov 29, 2023Updated 2 years ago
- ☆10Apr 28, 2023Updated 2 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Many peripherals in Verilog ready to use☆42Dec 29, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Video Stream Scaler☆40Jul 17, 2014Updated 11 years ago
- An implementation of the decoding of BCH codes resistant to timing attacks☆11Sep 18, 2020Updated 5 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- ☆14Dec 15, 2017Updated 8 years ago
- Cobra-W -> Cobra-RE 将进一步提升漏洞发现的准确性并降低漏报率(弃坑了)☆16Aug 15, 2020Updated 5 years ago
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 11 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆13Dec 16, 2020Updated 5 years ago
- An automatic speaker recognition system built from digital signal processing tools, Vector Quantization and LBG algorithm☆10May 24, 2021Updated 4 years ago
- ☆15Jun 28, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆48Jul 18, 2020Updated 5 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆59Nov 30, 2022Updated 3 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- LUT LDPC is a collection of software tools to design and test LDPC decoders based on discrete message passing decoding using lookup table…☆16May 30, 2018Updated 7 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 5 months ago
- Polar coding, decoding, and testing☆13Oct 11, 2023Updated 2 years ago
- A list Viterbo algorithm for decoding PAC codes with various code constructions/rate-profiles☆11May 6, 2022Updated 3 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆11Mar 12, 2024Updated 2 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- Decoding of LDPC Codes Using the Information Bottleneck Method in Python☆17Dec 11, 2018Updated 7 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆141Jul 31, 2022Updated 3 years ago
- ☆17Jul 23, 2018Updated 7 years ago