ultraembedded / minispartan6-audioLinks
miniSpartan6+ (Spartan6) FPGA based MP3 Player
☆27Updated 6 years ago
Alternatives and similar repositories for minispartan6-audio
Users that are interested in minispartan6-audio are comparing it to the libraries listed below
Sorting:
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆67Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- ☆37Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆83Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA☆87Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆44Updated 4 years ago
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆150Updated 9 months ago
- Portable HyperRAM controller☆61Updated last year
- ULPI Link Wrapper (USB Phy Interface)☆34Updated 5 years ago
- Wishbone interconnect utilities☆44Updated last week
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- SDRAM controller with multiple wishbone slave ports☆29Updated 7 years ago
- USB serial device (CDC-ACM)☆43Updated 5 years ago
- MIPI DSI controller☆81Updated 3 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆59Updated 4 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- Demo projects for various Kintex FPGA boards☆65Updated 7 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆31Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆29Updated 4 years ago
- HDMI Out VHDL code for 7-series Xilinx FPGAs☆61Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆93Updated 3 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆27Updated 2 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆34Updated 10 months ago
- Re-coded Gowin GW1N primitives for Verilator use☆20Updated 3 years ago