Alternatives and similar repositories for 8bit-computer

Users that are interested in 8bit-computer are comparing it to the libraries listed below

• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆145Updated 10 years ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆50Updated last year
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆192Updated 3 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆142Updated 3 years ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆60Updated 5 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆121Updated 6 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated 2 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆90Updated 4 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆107Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆99Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆102Updated 2 months ago
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated last month
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆90Updated 7 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆115Updated 4 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆133Updated last month
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆174Updated 3 months ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆53Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆137Updated 6 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆137Updated 3 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆399Updated this week
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• TimRudy / uart-verilog
  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
  ☆33Updated 2 years ago
• wuhanstudio / nand2tetris-iverilog
  A 16-bit Hack CPU from scratch on FPGA.
  ☆53Updated 4 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• emilbiju / emil-risc-v
  32 bit RISC-V CPU implementation in Verilog
  ☆31Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆173Updated 12 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆78Updated last year
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆134Updated 3 years ago
• RISCV-MYTH-WORKSHOP / RISC-V-CPU-Core-using-TL-Verilog
  risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom
  ☆13Updated 4 years ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 5 years ago