Alternatives and similar repositories for 8bit-computer

Users that are interested in 8bit-computer are comparing it to the libraries listed below

• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆68Updated 2 years ago
• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆150Updated 10 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆150Updated 5 years ago
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆35Updated 3 years ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆198Updated 4 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆457Updated this week
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆133Updated 7 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆130Updated 3 months ago
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆117Updated 2 years ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆92Updated 7 years ago
• os-fpga / Virtual-FPGA-Lab
  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…
  ☆235Updated 6 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆162Updated 6 years ago
• Arlet / verilog-6502
  A Verilog HDL model of the MOS 6502 CPU
  ☆362Updated 2 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆111Updated last year
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆168Updated 4 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆113Updated 4 months ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆148Updated 2 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated last month
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆96Updated 10 months ago
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆56Updated 3 weeks ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆69Updated 6 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆41Updated 2 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆172Updated 5 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆165Updated 4 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• jamieiles / uart
  Verilog UART
  ☆187Updated 12 years ago
• TimRudy / uart-verilog
  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
  ☆38Updated 3 months ago
• wuhanstudio / nand2tetris-iverilog
  A 16-bit Hack CPU from scratch on FPGA.
  ☆59Updated 5 years ago