Alternatives and similar repositories for 8bit-computer

Users that are interested in 8bit-computer are comparing it to the libraries listed below

• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆150Updated 10 years ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆60Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆143Updated 5 years ago
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆35Updated 3 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆129Updated 7 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆435Updated last week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆126Updated last month
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆164Updated 4 years ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆187Updated last month
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• RISCV-MYTH-WORKSHOP / RISC-V-CPU-Core-using-TL-Verilog
  risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom
  ☆15Updated 5 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆96Updated 8 months ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆143Updated last month
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆159Updated 6 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated this week
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆41Updated 2 years ago
• Arlet / verilog-6502
  A Verilog HDL model of the MOS 6502 CPU
  ☆358Updated 2 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆274Updated 5 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆155Updated 4 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆112Updated 3 months ago
• TimRudy / uart-verilog
  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
  ☆38Updated last month
• digital-design-hq / Digital-Resources
  ☆64Updated 4 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆282Updated last year
• wuhanstudio / nand2tetris-iverilog
  A 16-bit Hack CPU from scratch on FPGA.
  ☆59Updated 5 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆394Updated 4 months ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆56Updated 2 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆304Updated 9 months ago