FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.
☆19Apr 26, 2017Updated 9 years ago
Alternatives and similar repositories for fpga-projects
Users that are interested in fpga-projects are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- A web experiment to see how well you can estimate a minute. Compare yourself against 140k+ attempts☆13Apr 12, 2025Updated last year
- Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board☆18Nov 17, 2021Updated 4 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 5 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Jan 16, 2026Updated 4 months ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 8 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 7 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- padavan profile for newifi mini☆10Nov 17, 2016Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A System Verilog/FPGA implementation of the Gigatron project.☆19Oct 29, 2018Updated 7 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- Read-only mirror of https://framagit.org/tuxor1337/springerdownload. Pull requests and issues on GitHub cannot be accepted and will be au…☆41Feb 12, 2023Updated 3 years ago
- Write ups for DRDO CTF☆10Jan 13, 2018Updated 8 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆29Nov 21, 2020Updated 5 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆39Sep 18, 2024Updated last year
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆35Mar 23, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 8 years ago
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 11 months ago
- A set of OpenWRT/LEDE packages that allow communication with and usage of Quantenna QTS1000 series AC wifi cards.☆13Feb 6, 2017Updated 9 years ago
- ☆48Apr 7, 2024Updated 2 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- Nspire I/O is a collection of text input/output functions for the TI-Nspire. It allows you to create console based applications.☆16Jun 23, 2021Updated 4 years ago
- "The most beautiful experience we can have is the mysterious. It is the fundamental emotion that stands at the cradle of true art and tru…☆21Jan 8, 2022Updated 4 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- ☆13Dec 5, 2016Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RSA is the algorithm used by modern computers to encrypt and decrypt messages. It is an asymmetric cryptographic algorithm. Asymmetric me…☆16Jul 4, 2018Updated 7 years ago
- Katana - Automatic CTF Challenge Solver in Python3☆12Mar 17, 2020Updated 6 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆47Jul 16, 2021Updated 4 years ago
- Simple CH347 SPI-NOR programmer☆17Oct 20, 2023Updated 2 years ago
- Poplar documentation☆14Jun 25, 2018Updated 7 years ago
- This is a DIY project in which I control a relay module using ESP8266 via WiFi through BLynk. The relay module can activate or deactivate…☆18Oct 1, 2020Updated 5 years ago
- Verilog implementation of PAL, NTSC and SECAM color encoding☆72Sep 2, 2025Updated 8 months ago