FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.
☆19Apr 26, 2017Updated 9 years ago
Alternatives and similar repositories for fpga-projects
Users that are interested in fpga-projects are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- A web experiment to see how well you can estimate a minute. Compare yourself against 140k+ attempts☆13Apr 12, 2025Updated last year
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 7 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 7 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 8 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- "I'm not interested in possible complexities. I regard song structure as a graph paper." ― Brian Eno☆35Nov 22, 2019Updated 6 years ago
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- This is what happens when you can't make the subject interesting enough for a student.☆34May 10, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- padavan profile for newifi mini☆10Nov 17, 2016Updated 9 years ago
- A System Verilog/FPGA implementation of the Gigatron project.☆19Oct 29, 2018Updated 7 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- A set of 10 challenges for Forensics workshop, VIDYUT'19☆15Jul 23, 2020Updated 6 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 8 years ago
- Write ups for DRDO CTF☆10Jan 13, 2018Updated 8 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- A set of OpenWRT/LEDE packages that allow communication with and usage of Quantenna QTS1000 series AC wifi cards.☆13Feb 6, 2017Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is a DIY project in which I control a relay module using ESP8266 via WiFi through BLynk. The relay module can activate or deactivate…☆18Oct 1, 2020Updated 5 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆123Jul 9, 2023Updated 3 years ago
- Nspire I/O is a collection of text input/output functions for the TI-Nspire. It allows you to create console based applications.☆16Jun 23, 2021Updated 5 years ago
- AES implementation on FPGA☆13Apr 17, 2016Updated 10 years ago
- ☆13Dec 5, 2016Updated 9 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- RSA is the algorithm used by modern computers to encrypt and decrypt messages. It is an asymmetric cryptographic algorithm. Asymmetric me…☆16Jul 4, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆31Aug 16, 2021Updated 4 years ago
- Analyzes the results of more than 4.57 million chess games in the Chess960 variant.☆14May 11, 2020Updated 6 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆37Mar 23, 2024Updated 2 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆29Mar 21, 2022Updated 4 years ago
- ☆10Jan 29, 2019Updated 7 years ago
- ☆11Jun 22, 2020Updated 6 years ago
- This is a code repo for previous projects in Digital Design & Verification☆19Jan 6, 2015Updated 11 years ago